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Merge branch 'feat/h4_psram' into 'master'

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psram: h4 support

Closes IDF-12351 and IDF-12350

See merge request espressif/esp-idf!40484
This commit is contained in:
Armando (Dou Yiwen)
2025-07-28 09:39:41 +00:00
parent 93655332e8 9be8dccef5
commit 9e2d857c9a
21 changed files with 1075 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+12
View File
@@ -87,6 +87,10 @@ config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_32M
bool
default y
@@ -699,6 +703,14 @@ config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
bool
default y
config SOC_SPIRAM_XIP_SUPPORTED
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+5 -1
View File
@@ -86,7 +86,7 @@
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12310
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32H4] IDF-12388
// #define SOC_SPIRAM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12351
#define SOC_SPIRAM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_32M 1
@@ -501,6 +501,10 @@
#define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
/*-------------------------- SPIRAM CAPS -------------------------------------*/
#define SOC_SPIRAM_XIP_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32h4/register/soc/spi_mem_c_reg.h
+101
View File
@@ -531,6 +531,107 @@ extern "C" {
#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U
#define SPI_CLOSE_AXI_INF_EN_S 31
/** SPI_MEM_CACHE_SCTRL_REG register
* SPI0 external RAM control register
* This register is only for internal debugging purposes. Do not use it in
* applications.
*/
#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40)
/** SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO; bitpos: [0]; default: 0;
* For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1:
* enable, 0:disable.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0))
#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S)
#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U
#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0
/** SPI_MEM_USR_SRAM_DIO : HRO; bitpos: [1]; default: 0;
* For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_USR_SRAM_DIO (BIT(1))
#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S)
#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U
#define SPI_MEM_USR_SRAM_DIO_S 1
/** SPI_MEM_USR_SRAM_QIO : HRO; bitpos: [2]; default: 0;
* For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_USR_SRAM_QIO (BIT(2))
#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S)
#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U
#define SPI_MEM_USR_SRAM_QIO_S 2
/** SPI_MEM_USR_WR_SRAM_DUMMY : HRO; bitpos: [3]; default: 0;
* For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write
* operations.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3))
#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S)
#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U
#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3
/** SPI_MEM_USR_RD_SRAM_DUMMY : HRO; bitpos: [4]; default: 1;
* For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
* operations.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4))
#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S)
#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U
#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4
/** SPI_MEM_CACHE_SRAM_USR_RCMD : HRO; bitpos: [5]; default: 1;
* For SPI0, In the external RAM mode cache read external RAM for user define command.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5))
#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S)
#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U
#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5
/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO; bitpos: [11:6]; default: 1;
* For SPI0, In the external RAM mode, it is the length in bits of read dummy phase.
* The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU
#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6
/** SPI_MEM_SRAM_ADDR_BITLEN : HRO; bitpos: [19:14]; default: 23;
* For SPI0, In the external RAM mode, it is the length in bits of address phase. The
* register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU
#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S)
#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU
#define SPI_MEM_SRAM_ADDR_BITLEN_S 14
/** SPI_MEM_CACHE_SRAM_USR_WCMD : HRO; bitpos: [20]; default: 1;
* For SPI0, In the external RAM mode cache write sram for user define command
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20))
#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S)
#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U
#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20
/** SPI_MEM_SRAM_OCT : HRO; bitpos: [21]; default: 0;
* reserved
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SRAM_OCT (BIT(21))
#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S)
#define SPI_MEM_SRAM_OCT_V 0x00000001U
#define SPI_MEM_SRAM_OCT_S 21
/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO; bitpos: [27:22]; default: 1;
* For SPI0, In the external RAM mode, it is the length in bits of write dummy phase.
* The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU
#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22
/** SPI_MEM_SRAM_CMD_REG register
* SPI0 external RAM mode control register
*/
components/soc/esp32h4/register/soc/spi_mem_c_struct.h
+184 -2
View File
@@ -323,6 +323,25 @@ typedef union {
uint32_t val;
} spi_mem_c_cache_fctrl_reg_t;
typedef union {
struct {
uint32_t usr_saddr_4byte : 1; /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
uint32_t mem_usr_sram_dio : 1; /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
uint32_t mem_usr_sram_qio : 1; /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
uint32_t usr_wr_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
uint32_t mem_usr_rd_sram_dummy : 1; /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
uint32_t mem_cache_sram_usr_rcmd : 1; /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
uint32_t mem_sram_rdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved12 : 2; /*reserved*/
uint32_t mem_sram_addr_bitlen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
uint32_t mem_cache_sram_usr_wcmd : 1; /*For SPI0, In the external RAM mode cache write sram for user define command*/
uint32_t sram_oct : 1; /*reserved*/
uint32_t sram_wdummy_cyclelen : 6; /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} spi_mem_c_cache_sctrl_reg_t;
/** Type of ddr register
* SPI0 flash DDR mode control register
*/
@@ -437,6 +456,38 @@ typedef union {
uint32_t val;
} spi_mem_c_clock_reg_t;
/** Type of mem_sram_clk register
* SPI0 external RAM clock control register
*/
typedef union {
struct {
/** mem_sclkcnt_l : HRO; bitpos: [7:0]; default: 3;
* For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_l:8;
/** mem_sclkcnt_h : HRO; bitpos: [15:8]; default: 1;
* For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_h:8;
/** mem_sclkcnt_n : HRO; bitpos: [23:16]; default: 3;
* For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk
* frequency is system/(spi_mem_c_clkcnt_N+1)
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclkcnt_n:8;
uint32_t reserved_24:7;
/** mem_sclk_equ_sysclk : HRO; bitpos: [31]; default: 0;
* For SPI0 external RAM interface, 1: spi_mem_c_clk is equal to system 0: spi_mem_c_clk
* is divided from system clock.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_sclk_equ_sysclk:1;
};
uint32_t val;
} spi_mem_c_sram_clk_reg_t;
/** Type of clock_gate register
* SPI0 clock gate register
*/
@@ -565,6 +616,135 @@ typedef union {
uint32_t val;
} spi_mem_c_sram_cmd_reg_t;
/** Type of mem_sram_drd_cmd register
* SPI0 external RAM DDR read command control register
*/
typedef union {
struct {
/** mem_cache_sram_usr_rd_cmd_value : HRO; bitpos: [15:0]; default: 0;
* For SPI0,When cache mode is enable it is the read command value of command phase
* for sram.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_cache_sram_usr_rd_cmd_value:16;
uint32_t reserved_16:12;
/** mem_cache_sram_usr_rd_cmd_bitlen : HRO; bitpos: [31:28]; default: 0;
* For SPI0,When cache mode is enable it is the length in bits of command phase for
* sram. The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4;
};
uint32_t val;
} spi_mem_c_sram_drd_cmd_reg_t;
/** Type of mem_sram_dwr_cmd register
* SPI0 external RAM DDR write command control register
*/
typedef union {
struct {
/** mem_cache_sram_usr_wr_cmd_value : HRO; bitpos: [15:0]; default: 0;
* For SPI0,When cache mode is enable it is the write command value of command phase
* for sram.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_cache_sram_usr_wr_cmd_value:16;
uint32_t reserved_16:12;
/** mem_cache_sram_usr_wr_cmd_bitlen : HRO; bitpos: [31:28]; default: 0;
* For SPI0,When cache mode is enable it is the in bits of command phase for sram.
* The register value shall be (bit_num-1).
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4;
};
uint32_t val;
} spi_mem_c_sram_dwr_cmd_reg_t;
/** Type of smem_ddr register
* SPI0 external RAM DDR mode control register
*/
typedef union {
struct {
/** smem_ddr_en : HRO; bitpos: [0]; default: 0;
* 1: in DDR mode, 0 in SDR mode
*/
uint32_t smem_ddr_en:1;
/** smem_var_dummy : HRO; bitpos: [1]; default: 0;
* Set the bit to enable variable dummy cycle in spi DDR mode.
*/
uint32_t smem_var_dummy:1;
/** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0;
* Set the bit to reorder rx data of the word in spi DDR mode.
*/
uint32_t smem_ddr_rdat_swp:1;
/** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0;
* Set the bit to reorder tx data of the word in spi DDR mode.
*/
uint32_t smem_ddr_wdat_swp:1;
/** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0;
* the bit is used to disable dual edge in command phase when DDR mode.
*/
uint32_t smem_ddr_cmd_dis:1;
/** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1;
* It is the minimum output data length in the DDR psram.
*/
uint32_t smem_outminbytelen:7;
/** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1;
* Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
* accesses to external RAM.
*/
uint32_t smem_tx_ddr_msk_en:1;
/** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1;
* Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
* accesses to external RAM.
*/
uint32_t smem_rx_ddr_msk_en:1;
/** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0;
* The delay number of data strobe which from memory based on SPI clock.
*/
uint32_t smem_usr_ddr_dqs_thd:7;
/** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0;
* 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when
* spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or
* SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and
* negative edge of SPI_DQS.
*/
uint32_t smem_ddr_dqs_loop:1;
uint32_t reserved_22:2;
/** smem_clk_diff_en : HRO; bitpos: [24]; default: 0;
* Set this bit to enable the differential SPI_CLK#.
*/
uint32_t smem_clk_diff_en:1;
uint32_t reserved_25:1;
/** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0;
* Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
*/
uint32_t smem_dqs_ca_in:1;
/** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0;
* Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0
* accesses flash or SPI1 accesses flash or sram.
*/
uint32_t smem_hyperbus_dummy_2x:1;
/** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0;
* Set this bit to invert SPI_DIFF when accesses to external RAM. .
*/
uint32_t smem_clk_diff_inv:1;
/** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0;
* Set this bit to enable octa_ram address out when accesses to external RAM, which
* means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1],
* 1'b0}.
*/
uint32_t smem_octa_ram_addr:1;
/** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0;
* Set this bit to enable HyperRAM address out when accesses to external RAM, which
* means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.
*/
uint32_t smem_hyperbus_ca:1;
uint32_t reserved_31:1;
};
uint32_t val;
} spi_smem_c_ddr_reg_t;
/** Type of smem_ddr register
* SPI0 external RAM DDR mode control register
*/
@@ -2523,9 +2703,11 @@ typedef struct {
volatile spi_mem_c_misc_reg_t misc;
uint32_t reserved_038;
volatile spi_mem_c_cache_fctrl_reg_t cache_fctrl;
uint32_t reserved_040;
volatile spi_mem_c_cache_sctrl_reg_t mem_cache_sctrl;
volatile spi_mem_c_sram_cmd_reg_t sram_cmd;
uint32_t reserved_048[3];
volatile spi_mem_c_sram_drd_cmd_reg_t mem_sram_drd_cmd;
volatile spi_mem_c_sram_dwr_cmd_reg_t mem_sram_dwr_cmd;
volatile spi_mem_c_sram_clk_reg_t mem_sram_clk;
volatile spi_mem_c_fsm_reg_t fsm;
uint32_t reserved_058[26];
volatile spi_mem_c_int_ena_reg_t int_ena;