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https://github.com/espressif/esp-idf.git
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refactor(cache): move cache profile counter support to hal
Move the cache profile counter type definitions to hal/cache_types.h so that esp_cache_cnt.h can use them without depending on the public soc header soc/cache_periph.h (which CI rejects as non-public). The remaining cache_periph.h header and its per-target cache_periph.c sources are moved from the soc component into the hal component, with the sources organized per target directory as usual for the hal component. Removes the soc/cache_periph.h dependency from esp_cache_cnt.h and hal/cache_ll.h by using hal/cache_periph.h instead.
This commit is contained in:
morris
@@ -46,6 +46,10 @@ else()
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endif()
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endif()
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if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/cache_periph.c")
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list(APPEND srcs "${target}/cache_periph.c")
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endif()
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if(NOT esp_tee_build AND NOT BOOTLOADER_BUILD)
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list(APPEND srcs "color_hal.c")
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@@ -0,0 +1,41 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/cache_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-C5 cache profile counter units.
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*
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* Single cache level shared by instructions and data (the flash/PSRAM
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* cache, 32-byte lines), with two request buses: bus0 carries instruction
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* fetches, bus1 carries data accesses. Counter semantics match the
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* ESP32-P4. The hit/miss/conflict counters use the BUS0/BUS1 register
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* names while the corresponding next-level counters use the DBUS0/DBUS1
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* names. Only the CPU request buses are exposed here.
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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{
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.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
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},
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},
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};
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@@ -13,7 +13,7 @@
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#include "soc/cache_struct.h"
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#include "soc/ext_mem_defs.h"
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#include "rom/cache.h"
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#include "soc/cache_periph.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32c5/rom/cache.h"
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@@ -0,0 +1,40 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/extmem_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-C6 cache profile counter units.
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*
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* Single cache level shared by instructions and data (the flash cache,
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* 32-byte lines), with one instruction bus and one data bus. Counter
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* semantics match the ESP32-P4. There is one next-level counter per bus
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* (no read/write split), mapped here to line_fills. The cache is
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* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
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* so there are no write-back counters.
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = EXTMEM_L1_IBUS_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = EXTMEM_L1_IBUS_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG,
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},
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},
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{
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.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = EXTMEM_L1_DBUS_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = EXTMEM_L1_DBUS_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG,
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},
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},
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};
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@@ -12,7 +12,7 @@
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/cache_periph.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32c6/rom/cache.h"
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@@ -0,0 +1,40 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/cache_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-C61 cache profile counter units.
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*
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* Single cache level shared by instructions and data (the flash/PSRAM
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* cache), with two request buses: bus0 carries instruction fetches, bus1
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* carries data accesses (same bus arrangement as the ESP32-C5). bus0's
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* next-level counters use the BUS0 register names while bus1's use the
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* DBUS1 names.
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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{
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.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
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},
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},
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};
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@@ -12,7 +12,7 @@
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#include "soc/cache_reg.h"
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#include "soc/cache_struct.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/cache_periph.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32c61/rom/cache.h"
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@@ -0,0 +1,40 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/cache_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-H2 cache profile counter units.
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*
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* Single cache level shared by instructions and data (the flash cache,
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* 32-byte lines), with two request buses: bus0 carries instruction
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* fetches, bus1 carries data accesses. There is one next-level counter
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* per bus (no read/write split), mapped here to line_fills. The cache is
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* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
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* so there are no write-back counters.
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG,
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},
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},
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{
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.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG,
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},
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},
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};
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@@ -11,7 +11,7 @@
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/cache_periph.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32h2/rom/cache.h"
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@@ -0,0 +1,39 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/cache_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-H21 cache profile counter units.
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*
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* Single cache level shared by instructions and data (the flash cache),
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* with two request buses: bus0 carries instruction fetches, bus1 carries
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* data accesses (same bus arrangement as the ESP32-C5). The cache is
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* read-only (no PSRAM, no write-back — see SOC_CACHE_WRITEBACK_SUPPORTED),
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* so no write-back counters are exposed.
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-ibus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS0_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS0_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS0_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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{
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.name = "l1-cache-dbus", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_BUS1_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_BUS1_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_BUS1_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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};
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@@ -12,7 +12,7 @@
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#include "soc/cache_reg.h"
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#include "soc/cache_struct.h"
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#include "soc/ext_mem_defs.h"
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#include "soc/cache_periph.h"
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#include "hal/cache_periph.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "rom/cache.h"
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@@ -0,0 +1,58 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/cache_reg.h"
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#include "hal/cache_periph.h"
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/*
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* ESP32-H4 cache profile counter units.
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*
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* Single cache level (the flash/PSRAM cache); each core accesses it
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* through an instruction bus (ibus0/ibus1) and a data bus (dbus0/dbus1),
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* each with hit/miss/conflict/next-level counters (next-level write
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* counters on the data buses only).
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*/
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const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
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{
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.name = "l1-cache-inst-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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{
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.name = "l1-cache-inst-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
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},
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},
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{
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.name = "l1-cache-data-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
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.counter_reg = {
|
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
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},
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},
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{
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.name = "l1-cache-data-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
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.counter_reg = {
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[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
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[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
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[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
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},
|
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},
|
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};
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@@ -12,7 +12,7 @@
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#include "soc/cache_reg.h"
|
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#include "soc/cache_struct.h"
|
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#include "soc/ext_mem_defs.h"
|
||||
#include "soc/cache_periph.h"
|
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#include "hal/cache_periph.h"
|
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#include "hal/cache_types.h"
|
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#include "hal/assert.h"
|
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#include "rom/cache.h"
|
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@@ -0,0 +1,77 @@
|
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/*
|
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-P4 cache profile counter units.
|
||||
*
|
||||
* Topology: per-core L1 instruction caches (ibus0/ibus1) and a shared L1
|
||||
* data cache with one port per core (dbus0/dbus1). The L2 (flash/PSRAM)
|
||||
* cache reports all instruction traffic on its ibus0 counters and all data
|
||||
* traffic on its dbus0 counters, regardless of the originating core.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-icache-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-icache-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-dcache-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-dcache-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l2-cache-inst", .level = 2, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = -1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L2_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L2_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l2-cache-data", .level = 2, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = -1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L2_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L2_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -12,7 +12,7 @@
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/cache_periph.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/config.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/cache_reg.h"
|
||||
#include "hal/cache_periph.h"
|
||||
|
||||
/*
|
||||
* ESP32-S31 cache profile counter units.
|
||||
*
|
||||
* The register layout matches the ESP32-P4: per-bus hit/miss/conflict and
|
||||
* next-level read/write counters, with the same counter semantics. There
|
||||
* is a single cache level (the flash/PSRAM cache, 64-byte lines); each
|
||||
* core accesses it through an instruction bus (ibus0/ibus1) and a data
|
||||
* bus (dbus0/dbus1). Only the CPU request buses are exposed here.
|
||||
*/
|
||||
|
||||
const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM] = {
|
||||
{
|
||||
.name = "l1-cache-inst-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-inst-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_INST, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_IBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_IBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core0", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 0,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS0_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS0_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
{
|
||||
.name = "l1-cache-data-core1", .level = 1, .traffic = CACHE_PROFILE_TRAFFIC_DATA, .core_id = 1,
|
||||
.counter_reg = {
|
||||
[CACHE_PROFILE_COUNTER_HIT] = CACHE_L1_DBUS1_ACS_HIT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_MISS] = CACHE_L1_DBUS1_ACS_MISS_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_CONFLICT] = CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_RD] = CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG,
|
||||
[CACHE_PROFILE_COUNTER_NXTLVL_WR] = CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG,
|
||||
},
|
||||
},
|
||||
};
|
||||
@@ -12,7 +12,7 @@
|
||||
#include "soc/cache_reg.h"
|
||||
#include "soc/cache_struct.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
#include "soc/cache_periph.h"
|
||||
#include "hal/cache_periph.h"
|
||||
#include "hal/cache_types.h"
|
||||
#include "hal/assert.h"
|
||||
#include "esp32s31/rom/cache.h"
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/cache_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if SOC_CACHE_CNT_SUPPORTED
|
||||
/**
|
||||
* @brief Description of one cache profile counter unit
|
||||
*
|
||||
* A unit is one set of counters observing one traffic stream, e.g. the
|
||||
* instruction fetches of core 0 into the L1 cache.
|
||||
*/
|
||||
typedef struct {
|
||||
const char *name; /*!< Short human-readable name */
|
||||
uint8_t level; /*!< Cache level (1 or 2) */
|
||||
cache_profile_traffic_t traffic; /*!< Kind of traffic observed */
|
||||
int8_t core_id; /*!< Originating core, -1 if unknown/mixed */
|
||||
uint32_t counter_reg[CACHE_PROFILE_COUNTER_MAX]; /*!< Counter registers; 0 if the unit
|
||||
does not have that counter */
|
||||
} cache_profile_counter_unit_t;
|
||||
|
||||
extern const cache_profile_counter_unit_t cache_periph_profile_counter_units[SOC_CACHE_CNT_UNITS_NUM];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -6,12 +6,34 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Kind of traffic observed by a cache profile counter unit
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_PROFILE_TRAFFIC_INST, /*!< Instruction fetches */
|
||||
CACHE_PROFILE_TRAFFIC_DATA, /*!< Data accesses */
|
||||
CACHE_PROFILE_TRAFFIC_UNIFIED, /*!< Mixed/unknown (unified request bus) */
|
||||
} cache_profile_traffic_t;
|
||||
|
||||
/**
|
||||
* @brief One of the counters of a cache profile counter unit
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_PROFILE_COUNTER_HIT, /*!< Completed accesses ("hit" counter) */
|
||||
CACHE_PROFILE_COUNTER_MISS, /*!< Miss stall events ("miss" counter) */
|
||||
CACHE_PROFILE_COUNTER_CONFLICT, /*!< Requester conflicts */
|
||||
CACHE_PROFILE_COUNTER_NXTLVL_RD, /*!< Line fills from the next level */
|
||||
CACHE_PROFILE_COUNTER_NXTLVL_WR, /*!< Write-backs to the next level */
|
||||
CACHE_PROFILE_COUNTER_MAX,
|
||||
} cache_profile_counter_t;
|
||||
|
||||
typedef enum {
|
||||
CACHE_TYPE_DATA,
|
||||
CACHE_TYPE_INSTRUCTION,
|
||||
|
||||
Reference in New Issue
Block a user