feat(phy): add check for required clock bits during phy enable

2026-10-02 03:00:34 +03:00 · 2025-12-29 16:49:27 +08:00
parent ea2829f856
commit 9dc2dc8d1b
23 changed files with 212 additions and 1 deletions
@@ -298,6 +298,12 @@ static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, b
    }
 }

+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_clk_conf1_get(modem_syscon_dev_t *hw)
+{
+    return hw->clk_conf1.val;
+}
+
 __attribute__((always_inline))
 static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
 {