Merge branch 'feature/chip764_power_glitch_support' into 'master'

feat(s31): bootloader power glitch reset config

See merge request espressif/esp-idf!49050

components/soc/esp32s31/include/soc/regi2c_bias.h

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_bias.h
+ * @brief Register definitions for bias
+ *
+ * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * rtc_clk_init function in esp32s31/rtc_clk_init.c.
+ */
+
+#define I2C_BIAS        0x6A
+#define I2C_BIAS_HOSTID 0
+
+#define I2C_BIAS_DREG_1P6       0
+#define I2C_BIAS_DREG_1P6_MSB   3
+#define I2C_BIAS_DREG_1P6_LSB   0
+
+#define I2C_BIAS_DREG_1P1       0
+#define I2C_BIAS_DREG_1P1_MSB   7
+#define I2C_BIAS_DREG_1P1_LSB   4
+
+#define I2C_BIAS_DREG_1P1_PVT       1
+#define I2C_BIAS_DREG_1P1_PVT_MSB   3
+#define I2C_BIAS_DREG_1P1_PVT_LSB   0
+
+#define I2C_BIAS_DREG_2P2_PVT       1
+#define I2C_BIAS_DREG_2P2_PVT_MSB   7
+#define I2C_BIAS_DREG_2P2_PVT_LSB   4

components/soc/esp32s31/include/soc/regi2c_saradc.h

@@ -62,6 +62,38 @@
 #define ADC_SARADC_ENT_TSENS_ADDR_MSB       0x2
 #define ADC_SARADC_ENT_TSENS_ADDR_LSB       0x2
 
+#define POWER_GLITCH_XPD_VDET_PERIF         10
+#define POWER_GLITCH_XPD_VDET_PERIF_MSB     0
+#define POWER_GLITCH_XPD_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_XPD_VDET_VDDPST        10
+#define POWER_GLITCH_XPD_VDET_VDDPST_MSB    1
+#define POWER_GLITCH_XPD_VDET_VDDPST_LSB    1
+
+#define POWER_GLITCH_XPD_VDET_PLLBB         10
+#define POWER_GLITCH_XPD_VDET_PLLBB_MSB     2
+#define POWER_GLITCH_XPD_VDET_PLLBB_LSB     2
+
+#define POWER_GLITCH_XPD_VDET_PLL           10
+#define POWER_GLITCH_XPD_VDET_PLL_MSB       3
+#define POWER_GLITCH_XPD_VDET_PLL_LSB       3
+
+#define POWER_GLITCH_MODE_VDET_PERIF        10
+#define POWER_GLITCH_MODE_VDET_PERIF_MSB    4
+#define POWER_GLITCH_MODE_VDET_PERIF_LSB    4
+
+#define POWER_GLITCH_MODE_VDET_VDDPST       10
+#define POWER_GLITCH_MODE_VDET_VDDPST_MSB   5
+#define POWER_GLITCH_MODE_VDET_VDDPST_LSB   5
+
+#define POWER_GLITCH_MODE_VDET_PLLBB        10
+#define POWER_GLITCH_MODE_VDET_PLLBB_MSB    6
+#define POWER_GLITCH_MODE_VDET_PLLBB_LSB    6
+
+#define POWER_GLITCH_MODE_VDET_PLL          10
+#define POWER_GLITCH_MODE_VDET_PLL_MSB      7
+#define POWER_GLITCH_MODE_VDET_PLL_LSB      7
+
 #define POWER_GLITCH_DREF_VDET_PERIF         11
 #define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
 #define POWER_GLITCH_DREF_VDET_PERIF_LSB     0