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feat(hal/sha): use RCC atomic block to enable/reset the SHA peripheral

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This commit is contained in:
harshal.patil
2024-03-27 11:23:30 +05:30
parent 211a2a5477
commit 9cd10e196b
18 changed files with 375 additions and 55 deletions
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components/esp_hw_support/esp_ds.c
+15 -4
View File
@@ -29,6 +29,7 @@
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/sha_ll.h"
#endif /* !CONFIG_IDF_TARGET_ESP32S2 */
#if CONFIG_IDF_TARGET_ESP32S2
@@ -270,7 +271,10 @@ static void ds_acquire_enable(void)
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@@ -288,7 +292,9 @@ static void ds_disable_release(void)
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
@@ -445,7 +451,10 @@ esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
aes_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
ets_ds_data_t *ds_data = (ets_ds_data_t *) data;
const ets_ds_p_data_t *ds_plain_data = (const ets_ds_p_data_t *) p_data;
@@ -456,7 +465,9 @@ esp_err_t esp_ds_encrypt_params(esp_ds_data_t *data,
result = ESP_ERR_INVALID_ARG;
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
AES_RCC_ATOMIC() {
aes_ll_enable_bus_clock(false);
components/esp_hw_support/esp_hmac.c
+8 -2
View File
@@ -21,6 +21,7 @@
#include "hal/ds_ll.h"
#include "hal/hmac_hal.h"
#include "hal/hmac_ll.h"
#include "hal/sha_ll.h"
#include "esp_private/periph_ctrl.h"
#endif
@@ -75,7 +76,10 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
hmac_ll_reset_register();
}
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
}
DS_RCC_ATOMIC() {
ds_ll_enable_bus_clock(true);
@@ -146,7 +150,9 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
ds_ll_enable_bus_clock(false);
}
periph_module_disable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC() {
sha_ll_enable_bus_clock(false);
}
HMAC_RCC_ATOMIC() {
hmac_ll_enable_bus_clock(false);
components/esp_hw_support/include/esp_private/esp_crypto_lock_internal.h
+2
View File
@@ -20,6 +20,7 @@ extern "C" {
#define DS_RCC_ATOMIC()
#define ECDSA_RCC_ATOMIC()
#define AES_RCC_ATOMIC()
#define SHA_RCC_ATOMIC()
#else /* !SOC_RCC_IS_INDEPENDENT */
#define MPI_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define ECC_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
@@ -27,6 +28,7 @@ extern "C" {
#define DS_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define ECDSA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define AES_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#define SHA_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#endif /* SOC_RCC_IS_INDEPENDENT */
#ifdef __cplusplus