Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'contrib/github_pr_13020' into 'master'

Browse Source 
fix (esp_lcd): Don't assume panels are 16bit in VSYNC restart logic (GitHub PR)

Closes IDFGH-11941

See merge request espressif/esp-idf!28593
This commit is contained in:
morris
2024-01-31 18:49:51 +08:00
parent 8d558a0ea7 b10dec96c5
commit 9bdd431fe3
3 changed files with 25 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32p4/include/hal/lcd_ll.h
+1
View File
@@ -28,6 +28,7 @@ extern "C" {
#define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width
#define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width
#define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width
#define LCD_LL_FIFO_DEPTH 8 // Async FIFO depth
/**
* @brief LCD data byte swizzle mode
components/hal/esp32s3/include/hal/lcd_ll.h
+1
View File
@@ -28,6 +28,7 @@ extern "C" {
#define LCD_LL_CLK_FRAC_DIV_N_MAX 256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width
#define LCD_LL_CLK_FRAC_DIV_AB_MAX 64 // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width
#define LCD_LL_PCLK_DIV_MAX 64 // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width
#define LCD_LL_FIFO_DEPTH 16 // Async FIFO depth
/**
* @brief LCD data byte swizzle mode