feat(usb): add ESP32-S31 DWC/UTMI support

Add ESP32-S31 USB DWC/UTMI LL headers, SoC register structures, peripheral
descriptors, capabilities, and linker mappings so the HS OTG controller and
UTMI PHY can be built in esp_hal_usb.

Introduce SOC_USB_FSLS_PHY_NUM on USB-OTG targets to separate FSLS USB_WRAP
support from OTG/UTMI support. Use it to gate usb_wrap, the USB PHY driver,
docs, and example build rules on targets without an FSLS PHY.

Also add UTMI data pulldown control to the HAL, clear the boot-time DWC
suspend state on ESP32-S31, alias the legacy internal PHY target to UTMI for
backward compatibility, and extend usb_phy tests for UTMI-only targets.

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -803,6 +803,10 @@ config SOC_USB_OTG_PERIPH_NUM
     int
     default 1
 
+config SOC_USB_FSLS_PHY_NUM
+    int
+    default 1
+
 config SOC_SHA_DMA_MAX_BUFFER_SIZE
     int
     default 3968

components/soc/esp32s3/include/soc/soc_caps.h

@@ -337,6 +337,7 @@
 
 /*-------------------------- USB CAPS ----------------------------------------*/
 #define SOC_USB_OTG_PERIPH_NUM          (1U)
+#define SOC_USB_FSLS_PHY_NUM            (1U)
 
 /*--------------------------- SHA CAPS ---------------------------------------*/
 /* Max amount of bytes in a single DMA operation is 4095,