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feat(driver_spi): spi master support sleep retention(recovery)

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This commit is contained in:
wanckl
2025-12-23 13:54:21 +08:00
parent 2910e7de68
commit 9a93f402db
26 changed files with 449 additions and 279 deletions
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components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
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@@ -991,6 +991,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_SPI_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
components/soc/esp32c6/include/soc/retention_periph_defs.h
+2
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@@ -36,6 +36,7 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_RMT0 = 13,
SLEEP_RETENTION_MODULE_UART0 = 14,
SLEEP_RETENTION_MODULE_UART1 = 15,
SLEEP_RETENTION_MODULE_GPSPI2 = 16,
/* Modem module, which includes WiFi, BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_WIFI_MAC = 26,
@@ -62,6 +63,7 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_RMT0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_GPSPI2) ? true \
: false)
#ifdef __cplusplus
components/soc/esp32c6/include/soc/soc_caps.h
+1
View File
@@ -395,6 +395,7 @@
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
#define SOC_SPI_SUPPORT_SLEEP_RETENTION 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
#define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
components/soc/esp32c6/spi_periph.c
+45 -24
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,29 +13,6 @@
const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
{
// MSPI has dedicated iomux pins
.spiclk_out = -1,
.spiclk_in = -1,
.spid_out = -1,
.spiq_out = -1,
.spiwp_out = -1,
.spihd_out = -1,
.spid_in = -1,
.spiq_in = -1,
.spiwp_in = -1,
.spihd_in = -1,
.spics_out = {-1},
.spics_in = -1,
.spiclk_iomux_pin = -1,
.spid_iomux_pin = -1,
.spiq_iomux_pin = -1,
.spiwp_iomux_pin = -1,
.spihd_iomux_pin = -1,
.spics0_iomux_pin = -1,
.irq = -1,
.irq_dma = -1,
.module = -1,
.hw = NULL,
.func = -1,
}, {
.spiclk_out = FSPICLK_OUT_IDX,
.spiclk_in = FSPICLK_IN_IDX,
@@ -62,3 +39,47 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.func = SPI2_FUNC_NUM,
}
};
/**
* Backup registers in Light sleep: (total cnt 12)
*
* cmd
* addr
* ctrl
* clock
* user
* user1
* user2
* ms_dlen
* misc
* dma_conf
* dma_int_ena
* slave
*/
#define SPI_RETENTION_REGS_CNT 12
static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
#define SPI_REG_RETENTION_ENTRIES(num) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
REG_SPI_BASE(num), REG_SPI_BASE(num), \
SPI_RETENTION_REGS_CNT, 0, 0, \
spi_regs_map[0], spi_regs_map[1], \
spi_regs_map[2], spi_regs_map[3]), \
.owner = ENTRY(0) | ENTRY(2) }, \
/* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
SPI_DMA_INT_SET_REG(num), \
SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
UINT32_MAX, 1, 0), \
.owner = ENTRY(0) | ENTRY(2) }, \
}
static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2
const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi
{
.module_id = SLEEP_RETENTION_MODULE_GPSPI2,
.entry_array = spi2_regs_retention,
.array_size = ARRAY_SIZE(spi2_regs_retention),
},
};