From 9a6ab5c0a799be7fac0291a80c6760bc73664cc2 Mon Sep 17 00:00:00 2001 From: "yanzihan@espressif.com" Date: Mon, 19 Jan 2026 21:13:55 +0800 Subject: [PATCH] fix(esp_hw_support): adjust pvt prepare cost in sleep wakeup --- components/esp_hw_support/sleep_modes.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 7d39966de8f..6ee34c32726 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -163,9 +163,11 @@ #elif CONFIG_IDF_TARGET_ESP32C6 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) +#define PVT_REINIT_COST_US (60) #elif CONFIG_IDF_TARGET_ESP32C5 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) +#define PVT_REINIT_COST_US (25) #elif CONFIG_IDF_TARGET_ESP32C61 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107) @@ -1402,9 +1404,9 @@ esp_err_t esp_light_sleep_start(void) // Re-calibrate the RTC clock sleep_low_power_clock_calibration(false); + uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ; + uint32_t xtal_freq = rtc_clk_xtal_freq_get(); if (s_config.overhead_out_need_remeasure) { - uint32_t cur_cpu_freq = esp_clk_cpu_freq() / MHZ; - uint32_t xtal_freq = rtc_clk_xtal_freq_get(); if (cur_cpu_freq < xtal_freq) { s_config.sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US * xtal_freq / cur_cpu_freq; } else { @@ -1421,6 +1423,17 @@ esp_err_t esp_light_sleep_start(void) */ #if SOC_PMU_SUPPORTED int sleep_time_sw_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out; +#if CONFIG_ESP_ENABLE_PVT && !SOC_PVT_EN_WITH_SLEEP + /* PVT will only be enabled during the wake-up process if the CPU's clock source is PLL when the CPU goes to sleep. */ + if ((cur_cpu_freq > xtal_freq) +#if CONFIG_IDF_TARGET_ESP32C5 + /* On esp32c5, CPU 40m is divided from PLL160/240M */ + || (xtal_freq == SOC_XTAL_FREQ_48M && cur_cpu_freq == 40) +#endif + ) { + sleep_time_sw_adjustment += PVT_REINIT_COST_US; + } +#endif int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period); s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment; #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD