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change(soc): reset L2 Cache sync after config restore

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wuzhenghui
2025-11-04 16:03:28 +08:00
parent d4b3d01b4d
commit 9a5f1475e8
2 changed files with 6 additions and 2 deletions
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components/soc/esp32p4/include/soc/system_periph_retention.h
+1 -1
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@@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
* This is an internal function of the sleep retention driver, and is not * This is an internal function of the sleep retention driver, and is not
* useful for external use. * useful for external use.
*/ */
#define CACHE_RETENTION_LINK_LEN 8 #define CACHE_RETENTION_LINK_LEN 10
extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN]; extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
/** /**
components/soc/esp32p4/system_retention_periph.c
+5 -1
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@@ -69,7 +69,11 @@ const regdma_entries_config_t cache_regs_retention[] = {
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) }, [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) }, [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) }, [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) }, [7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
// Reset L2 CACHE SYNC
[8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x09), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
}; };
_Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions"); _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");