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ci(system): fixing misc core system H4 tests

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This commit is contained in:
Marius Vikhammer
2026-05-12 17:12:30 +08:00
parent 3a26929cb6
commit 96333567e8
3 changed files with 70 additions and 5 deletions
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tools/test_apps/system/.build-test-rules.yml
-4
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@@ -58,10 +58,6 @@ tools/test_apps/system/eh_frame:
reason: Only relevant for riscv targets reason: Only relevant for riscv targets
tools/test_apps/system/esp_intr_dump: tools/test_apps/system/esp_intr_dump:
disable_test:
- if: IDF_TARGET == "esp32h4"
temporary: true
reason: cannot pass # TODO: IDF-15603
tools/test_apps/system/flash_auto_suspend_iram_reduction: tools/test_apps/system/flash_auto_suspend_iram_reduction:
disable: disable:
tools/test_apps/system/esp_intr_dump/expected_output/esp32h4.txt
+70
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@@ -0,0 +1,70 @@
CPU 0 interrupt status:
Int Level Type Status
0 1 Level Shared: LP_RTC_TIMER
1 1 Level Used: MSPI
2 1 Level Used: CPU_FROM_CPU_0
3 1 Level Used: SYSTIMER_TARGET0
4 1 Level Used: TG0_WDT
5 1 Level Used: UART0
6 * * Reserved
7 * * Free
8 * * Free
9 * * Free
10 * * Free
11 * * Free
12 * * Free
13 * * Free
14 * * Free
15 * * Free
16 * * Free
17 * * Free
18 * * Free
19 * * Free
20 * * Free
21 * * Free
22 * * Free
23 * * Free
24 * * Reserved
25 * * Reserved
26 * * Free
27 * * Reserved
28 * * Reserved
29 * * Free
30 * * Free
31 * * Free
CPU 1 interrupt status:
Int Level Type Status
0 ? ? Used: CPU_FROM_CPU_1
1 ? ? Used: SYSTIMER_TARGET1
2 * * Free
3 * * Free
4 * * Free
5 * * Free
6 * * Reserved
7 * * Free
8 * * Free
9 * * Free
10 * * Free
11 * * Free
12 * * Free
13 * * Free
14 * * Free
15 * * Free
16 * * Free
17 * * Free
18 * * Free
19 * * Free
20 * * Free
21 * * Free
22 * * Free
23 * * Free
24 * * Reserved
25 * * Reserved
26 * * Free
27 * * Reserved
28 * * Reserved
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 46
Shared interrupts: 1
tools/test_apps/system/esp_intr_dump/pytest_esp_intr_dump.py
-1
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@@ -48,7 +48,6 @@ def test_esp_intr_dump_shared(dut: Dut) -> None:
# TODO: IDF-9512, Update the expected output of dual core RISC-V chips when the issue is resolved # TODO: IDF-9512, Update the expected output of dual core RISC-V chips when the issue is resolved
@pytest.mark.generic @pytest.mark.generic
@idf_parametrize('target', ['supported_targets'], indirect=['target']) @idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='cannot pass') # TODO: IDF-15603
def test_esp_intr_dump_expected_output(dut: Dut) -> None: def test_esp_intr_dump_expected_output(dut: Dut) -> None:
dut.expect_exact(PROMPT, timeout=30) dut.expect_exact(PROMPT, timeout=30)
dut.write('intr_dump\n') dut.write('intr_dump\n')