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feat(parlio): support parlio on esp32h4

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This commit is contained in:
Chen Jichang
2026-01-13 17:07:28 +08:00
committed by Chen Ji Chang
parent b685c0e733
commit 954a7619a2
25 changed files with 1289 additions and 396 deletions
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components/esp_driver_parlio/test_apps/parlio/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- | -------- |
components/esp_driver_parlio/test_apps/parlio/main/test_board.h
+12
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@@ -56,6 +56,18 @@ extern "C" {
#define TEST_DATA5_GPIO 11
#define TEST_DATA6_GPIO 26
#define TEST_DATA7_GPIO 12
#elif CONFIG_IDF_TARGET_ESP32H4
#define TEST_CLK_GPIO 15
#define TEST_EXT_CLK_GPIO 16
#define TEST_VALID_GPIO 17
#define TEST_DATA0_GPIO 0
#define TEST_DATA1_GPIO 1
#define TEST_DATA2_GPIO 2
#define TEST_DATA3_GPIO 3
#define TEST_DATA4_GPIO 4
#define TEST_DATA5_GPIO 5
#define TEST_DATA6_GPIO 13
#define TEST_DATA7_GPIO 14
#elif CONFIG_IDF_TARGET_ESP32P4
#define TEST_CLK_GPIO 33
#define TEST_EXT_CLK_GPIO 34
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+3 -3
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@@ -223,13 +223,13 @@ static void level_delimiter_sender_task_spi(void *args)
// Connect SPI signals to parlio rx signals
connect_signal_internally(TEST_CLK_GPIO,
spi_periph_signal[TEST_SPI_HOST].spiclk_out,
parlio_periph_signals.groups[0].rx_units[0].clk_in_sig);
soc_parlio_signals[0].rx_units[0].clk_in_sig);
connect_signal_internally(TEST_VALID_GPIO,
spi_periph_signal[TEST_SPI_HOST].spics_out[0],
parlio_periph_signals.groups[0].rx_units[0].data_sigs[TEST_VALID_SIG]);
soc_parlio_signals[0].rx_units[0].data_sigs[TEST_VALID_SIG]);
connect_signal_internally(TEST_DATA0_GPIO,
spi_periph_signal[TEST_SPI_HOST].spid_out,
parlio_periph_signals.groups[0].rx_units[0].data_sigs[0]);
soc_parlio_signals[0].rx_units[0].data_sigs[0]);
// Prepare the data the be transmitted
uint8_t *data = NULL;