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feat(ppa): add sleep retention support for DMA2D and PPA

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This commit is contained in:
Song Ruo Jing
2026-07-03 20:36:32 +08:00
parent 69d6deb7e6
commit 9516083cb1
20 changed files with 569 additions and 118 deletions
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components/soc/CMakeLists.txt
+4
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@@ -51,6 +51,10 @@ if(CONFIG_SOC_DMA2D_SUPPORTED)
list(APPEND srcs "${target_folder}/dma2d_periph.c")
endif()
if(CONFIG_SOC_PPA_SUPPORTED)
list(APPEND srcs "${target_folder}/ppa_periph.c")
endif()
if(CONFIG_SOC_GPSPI_SUPPORTED)
list(APPEND srcs "${target_folder}/spi_periph.c")
endif()
components/soc/esp32p4/dma2d_periph.c
+31 -1
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@@ -1,10 +1,11 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dma2d_periph.h"
#include "soc/dma2d_reg.h"
#include "soc/interrupts.h"
const dma2d_signal_conn_t dma2d_periph_signals = {
@@ -22,3 +23,32 @@ const dma2d_signal_conn_t dma2d_periph_signals = {
}
}
};
/** DMA2D Registers to be saved during sleep retention
*
* DMA2D driver is implemented in the way that channels are used as a pool,
* therefore, only general registers are needed to be saved during sleep retention.
*
* DMA2D_RST_CONF_REG,
* DMA2D_INTR_MEM_START_ADDR_REG, DMA2D_INTR_MEM_END_ADDR_REG, DMA2D_EXTR_MEM_START_ADDR_REG, DMA2D_EXTR_MEM_END_ADDR_REG
* DMA2D_OUT_ARB_CONFIG_REG, DMA2D_IN_ARB_CONFIG_REG
*/
#define DMA2D_RETENTION_REGS_CNT 7
#define DMA2D_RETENTION_REGS_BASE DMA2D_RST_CONF_REG
static const uint32_t dma2d_regs_map[4] = {0x7f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t dma2d_regdma_entries[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_DMA2D_LINK(0x00),
DMA2D_RETENTION_REGS_BASE, DMA2D_RETENTION_REGS_BASE,
DMA2D_RETENTION_REGS_CNT, 0, 0,
dma2d_regs_map[0], dma2d_regs_map[1],
dma2d_regs_map[2], dma2d_regs_map[3]),
.owner = ENTRY(0),
},
};
const dma2d_reg_retention_info_t dma2d_reg_retention_info = {
.module = SLEEP_RETENTION_MODULE_DMA2D,
.regdma_entry_array = dma2d_regdma_entries,
.array_size = ARRAY_SIZE(dma2d_regdma_entries),
};
components/soc/esp32p4/include/soc/retention_periph_defs.h
+5 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -33,6 +33,8 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_UART2 = 11,
SLEEP_RETENTION_MODULE_UART3 = 12,
SLEEP_RETENTION_MODULE_UART4 = 13,
SLEEP_RETENTION_MODULE_DMA2D = 41,
SLEEP_RETENTION_MODULE_PPA = 42,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
@@ -51,6 +53,8 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_UART2) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART3) ? true \
: ((m) == SLEEP_RETENTION_MODULE_UART4) ? true \
: ((m) == SLEEP_RETENTION_MODULE_DMA2D) ? true \
: ((m) == SLEEP_RETENTION_MODULE_PPA) ? true \
: false)
#ifdef __cplusplus
components/soc/esp32p4/ppa_periph.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ppa_periph.h"
#include "soc/ppa_reg.h"
/** PPA Registers to be saved during sleep retention
*
* For CLUT mem, we shall choose not to power down the CLUT mem domain; Otherwise, there are two blocks of memory that needs to be restored by writing to mem addr directly.
* Since PPA driver is operation based, most of the registers are configured per operation, so no need to save/restore.
*
* PPA_CLUT_CONF_REG,
* PPA_INT_ENA_REG,
* PPA_SR_MEM_PD_REG, PPA_REG_CONF_REG, PPA_SRAM_CTRL_REG,
* PPA_RGB2GRAY_REG (> rev3 only, but ok to include it for < rev3 chips)
*/
#define PPA_RETENTION_REGS_CNT 6
#define PPA_RETENTION_REGS_BASE PPA_CLUT_CONF_REG
static const uint32_t ppa_regs_map[4] = {0x1800009, 0x9, 0x0, 0x0};
static const regdma_entries_config_t ppa_regdma_entries[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PPA_LINK(0x00),
PPA_RETENTION_REGS_BASE, PPA_RETENTION_REGS_BASE,
PPA_RETENTION_REGS_CNT, 0, 0,
ppa_regs_map[0], ppa_regs_map[1],
ppa_regs_map[2], ppa_regs_map[3]),
.owner = ENTRY(0),
},
};
const ppa_reg_retention_info_t ppa_reg_retention_info = {
.module = SLEEP_RETENTION_MODULE_PPA,
.regdma_entry_array = ppa_regdma_entries,
.array_size = ARRAY_SIZE(ppa_regdma_entries),
};
components/soc/esp32p4/system_retention_periph.c
+5
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@@ -26,8 +26,13 @@
#include "soc/pvt_reg.h"
/* Interrupt Matrix Registers Context */
#if (CONFIG_ESP_REV_MIN_FULL < 300)
#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_CLOCK_GATE_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1)
#else
#define N_REGS_INTR_CORE0() (((INTERRUPT_CORE0_INTR_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE0_BASE) / 4) + 1)
#define N_REGS_INTR_CORE1() (((INTERRUPT_CORE1_INTR_SIG_IDX_ASSERT_IN_SEC_REG - DR_REG_INTERRUPT_CORE1_BASE) / 4) + 1)
#endif
const regdma_entries_config_t intr_matrix_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x00), DR_REG_INTERRUPT_CORE0_BASE, DR_REG_INTERRUPT_CORE0_BASE, N_REGS_INTR_CORE0(), 0, 0), .owner = ENTRY(0) }, /* intr matrix */
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0x01), DR_REG_INTERRUPT_CORE1_BASE, DR_REG_INTERRUPT_CORE1_BASE, N_REGS_INTR_CORE1(), 0, 0), .owner = ENTRY(0) } /* intr matrix */
components/soc/include/soc/dma2d_periph.h
+16 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,6 +9,11 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#if SOC_PAU_SUPPORTED
#include "soc/regdma.h"
#include "soc/retention_periph_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -22,6 +27,16 @@ typedef struct {
} dma2d_signal_conn_t;
extern const dma2d_signal_conn_t dma2d_periph_signals;
#if SOC_LIGHT_SLEEP_SUPPORTED
typedef struct {
const periph_retention_module_t module;
const regdma_entries_config_t *regdma_entry_array;
uint32_t array_size;
} dma2d_reg_retention_info_t;
extern const dma2d_reg_retention_info_t dma2d_reg_retention_info;
#endif
#endif
#ifdef __cplusplus
components/soc/include/soc/ppa_periph.h
+33
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@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#if SOC_PAU_SUPPORTED
#include "soc/regdma.h"
#include "soc/retention_periph_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PPA_SUPPORTED
#if SOC_LIGHT_SLEEP_SUPPORTED
typedef struct {
const periph_retention_module_t module;
const regdma_entries_config_t *regdma_entry_array;
uint32_t array_size;
} ppa_reg_retention_info_t;
extern const ppa_reg_retention_info_t ppa_reg_retention_info;
#endif
#endif
#ifdef __cplusplus
}
#endif
components/soc/include/soc/regdma.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,6 +53,9 @@ extern "C" {
#define REGDMA_TG0_TIMER_LINK(_pri) ((0x1C << 8) | _pri)
#define REGDMA_TG1_TIMER_LINK(_pri) ((0x1D << 8) | _pri)
#define REGDMA_GPSPI_LINK(_pri) ((0x1E << 8) | _pri)
#define REGDMA_PPA_LINK(_pri) ((0x2B << 8) | _pri)
#define REGDMA_DMA2D_LINK(_pri) ((0x2C << 8) | _pri)
#define REGDMA_MODEM_FE_LINK(_pri) ((0xFF << 8) | _pri)
#define REGDMA_LINK_PRI_SYS_CLK REGDMA_LINK_PRI_0
@@ -71,6 +74,8 @@ extern "C" {
#define REGDMA_LINK_PRI_I2C REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_UART REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_GPSPI REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_PPA REGDMA_LINK_PRI_GENERAL_PERIPH
#define REGDMA_LINK_PRI_DMA2D REGDMA_LINK_PRI_GENERAL_PERIPH
typedef enum {
REGDMA_LINK_PRI_0 = 0,