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refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV
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@@ -755,6 +755,10 @@ config SOC_CLK_OSC_SLOW_SUPPORTED
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bool
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default y
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config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
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bool
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default y
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config SOC_WIFI_HW_TSF
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bool
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default y
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@@ -21,7 +21,7 @@ extern "C" {
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*
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* 2) External 26/40MHz Crystal Clock: XTAL
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*
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
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*
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* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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@@ -82,9 +82,12 @@ typedef enum {
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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} soc_rtc_fast_clk_src_t;
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/**
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@@ -336,6 +336,8 @@
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#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< ESP32C2 only supports to connect an external oscillator, not a crystal */
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#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
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/*------------------------------------ WI-FI CAPS ------------------------------------*/
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#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
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#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */
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