refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV

This commit is contained in:
Song Ruo Jing
2024-11-04 12:37:17 +08:00
parent ce6085349f
commit 92ed77933b
38 changed files with 115 additions and 37 deletions
@@ -755,6 +755,10 @@ config SOC_CLK_OSC_SLOW_SUPPORTED
bool
default y
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y
config SOC_WIFI_HW_TSF
bool
default y
@@ -21,7 +21,7 @@ extern "C" {
*
* 2) External 26/40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -82,9 +82,12 @@ typedef enum {
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
} soc_rtc_fast_clk_src_t;
/**
@@ -336,6 +336,8 @@
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< ESP32C2 only supports to connect an external oscillator, not a crystal */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
/*------------------------------------ WI-FI CAPS ------------------------------------*/
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */