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synced 2026-10-02 03:00:34 +03:00
refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV
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@@ -726,7 +726,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4 //!< Main XTAL, divided by 4
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
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/**
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@@ -715,7 +715,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
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/**
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@@ -784,7 +784,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
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/**
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@@ -465,7 +465,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
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/**
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@@ -462,7 +462,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
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/**
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@@ -864,7 +864,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 4
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4 //!< Main XTAL, divided by 4
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 8 MHz RC oscillator
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/**
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@@ -842,7 +842,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
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* @brief RTC FAST_CLK frequency values
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*/
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typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2 //!< Main XTAL, divided by 2
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#define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST //!< Internal 17.5 MHz RC oscillator
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/**
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -177,23 +177,23 @@ uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
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uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
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{
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switch (clk_ll_rtc_fast_get_src()) {
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case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 //SOC_RTC_FAST_CLK_SRC_XTAL_D4
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
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#elif CONFIG_IDF_TARGET_ESP32P4 //SOC_RTC_FAST_CLK_SRC_XTAL
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return clk_hal_xtal_get_freq_mhz() * MHZ;
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#else //SOC_RTC_FAST_CLK_SRC_XTAL_D2
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
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#endif
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case SOC_RTC_FAST_CLK_SRC_RC_FAST:
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return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
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#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
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case SOC_RTC_FAST_CLK_SRC_LP_PLL:
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return clk_ll_lp_pll_get_freq_mhz() * MHZ;
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#endif
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#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
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#if SOC_CLK_LP_FAST_SUPPORT_XTAL
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case SOC_RTC_FAST_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz() * MHZ;
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#endif
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#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
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case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
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#endif
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#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
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case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
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return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
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#endif
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default:
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// Invalid clock source
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