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Merge branch 'fix/zol_reset_lcounter' into 'master'

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fix(xtensa): Reset zero overhead loop counter in ISRs

Closes IDF-15322

See merge request espressif/esp-idf!45865
This commit is contained in:
Konstantin Kondrashov
2026-04-29 12:44:00 +03:00
parent e684ca5183 a00bb2d1cb
commit 92bb2641b4
5 changed files with 143 additions and 13 deletions
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components/bt/controller/esp32/hli_vectors.S
+9 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <xtensa/coreasm.h>
#include <xtensa/corebits.h>
#include <xtensa/config/system.h>
#include "xtensa/config/core-isa.h"
#include "xtensa_context.h"
#include "sdkconfig.h"
#include "soc/soc.h"
@@ -87,12 +88,16 @@ xt_highint4:
s32i a2, a0, 4
rsr a2, XT_REG_SAR
s32i a2, a0, 8
#if XCHAL_HAVE_LOOPS
rsr a2, XT_REG_LBEG
s32i a2, a0, 12
rsr a2, XT_REG_LEND
s32i a2, a0, 16
rsr a2, XT_REG_LCOUNT
/* Save and disable active zero-overhead loop state while executing high-level ISR code. */
movi a2, 0
xsr a2, XT_REG_LCOUNT /* a2 = LCOUNT, LCOUNT = 0 */
s32i a2, a0, 20
#endif
rsr a2, EPC1
s32i a2, a0, 24
@@ -189,12 +194,14 @@ _highint4_stack_switch:
movi a0, _l4_save_ctx + SPECREG_OFFSET
l32i a2, a0, 8
wsr a2, XT_REG_SAR
#if XCHAL_HAVE_LOOPS
l32i a2, a0, 12
wsr a2, XT_REG_LBEG
l32i a2, a0, 16
wsr a2, XT_REG_LEND
l32i a2, a0, 20
wsr a2, XT_REG_LCOUNT
#endif
l32i a2, a0, 24
wsr a2, EPC1