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Merge branch 'feat/support_io_edge_wakeup' into 'master'

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feat(esp_hw_support): support rtc io edge wakeup sleep

Closes FCS-1880 and IDF-11812

See merge request espressif/esp-idf!48410
This commit is contained in:
Wu Zheng Hui
2026-05-20 19:37:35 +08:00
parent 0f2674f616 2f845ec76d
commit 91e66a8d19
38 changed files with 293 additions and 95 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_gpio/include/driver/gpio.h
+5 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -575,7 +575,10 @@ esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
*
* @param gpio_num GPIO number.
*
* @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
* @param intr_type GPIO wake-up type.
* - Always supported: GPIO_INTR_LOW_LEVEL, GPIO_INTR_HIGH_LEVEL
* - If SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED:
* GPIO_INTR_POSEDGE, GPIO_INTR_NEGEDGE, GPIO_INTR_ANYEDGE
*
* @note Called by the SDK. User shouldn't call this directly in the APP.
*
components/esp_driver_gpio/include/driver/rtc_io.h
+5 -4
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@@ -309,12 +309,13 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num);
/**
* @brief Enable wakeup from sleep mode using specific GPIO
* @param gpio_num GPIO number
* @param intr_type Wakeup on high level (GPIO_INTR_HIGH_LEVEL) or low level
* (GPIO_INTR_LOW_LEVEL)
* @param intr_type Wakeup trigger type:
* - Always supported: GPIO_INTR_HIGH_LEVEL, GPIO_INTR_LOW_LEVEL
* - If SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED:
* GPIO_INTR_POSEDGE, GPIO_INTR_NEGEDGE, GPIO_INTR_ANYEDGE
* @return
* - ESP_OK Success
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO, or intr_type is not
* one of GPIO_INTR_HIGH_LEVEL, GPIO_INTR_LOW_LEVEL.
* - ESP_ERR_INVALID_ARG The IO is not an RTC IO, or intr_type is not supported by the target.
*/
esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
components/esp_driver_gpio/src/gpio.c
+7
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@@ -1067,10 +1067,17 @@ esp_err_t gpio_wakeup_enable_on_hp_periph_powerdown_sleep(gpio_num_t gpio_num, g
ESP_LOGE(GPIO_TAG, "GPIO %d does not support wakeup on peripheral powerdown sleep", gpio_num);
return ESP_ERR_INVALID_ARG;
}
#if SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
if (intr_type == GPIO_INTR_DISABLE || intr_type > GPIO_INTR_HIGH_LEVEL) {
ESP_LOGE(GPIO_TAG, "invalid intr_type for wakeup, gpio_num:%u", gpio_num);
return ESP_ERR_INVALID_ARG;
}
#else
if ((intr_type != GPIO_INTR_LOW_LEVEL) && (intr_type != GPIO_INTR_HIGH_LEVEL)) {
ESP_LOGE(GPIO_TAG, "GPIO wakeup only supports level mode, but edge mode set. gpio_num:%u", gpio_num);
return ESP_ERR_INVALID_ARG;
}
#endif
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, true);
components/esp_driver_gpio/src/rtc_io.c
+2 -5
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@@ -16,9 +16,6 @@
#include "hal/rtc_io_hal.h"
#include "hal/rtc_io_periph.h"
#include "soc/soc_caps.h"
#if SOC_RTCIO_PIN_COUNT > 0
#include "hal/rtc_gpio_caps.h"
#endif
#if SOC_LP_GPIO_MATRIX_SUPPORTED
#include "soc/lp_gpio_pins.h"
#endif
@@ -320,11 +317,11 @@ esp_err_t rtc_gpio_isolate(gpio_num_t gpio_num)
esp_err_t rtc_gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
#if !RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED)
#if !SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) {
return ESP_ERR_INVALID_ARG; // Dont support this mode.
}
#endif //!RTC_GPIO_CAPS_GET(EDGE_WAKEUP_SUPPORTED)
#endif //!SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
RTCIO_ENTER_CRITICAL();
rtcio_hal_wakeup_enable(rtc_io_number_get(gpio_num), intr_type);
RTCIO_EXIT_CRITICAL();
components/esp_hal_gpio/esp32c5/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h
+10
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@@ -344,6 +344,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_GPIO.pinn[rtcio_num].pinn_int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_GPIO.pinn[rtcio_num].pinn_edge_wakeup_clr = 1;
}
/**
* Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/esp32c6/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32c6/include/hal/rtc_io_ll.h
+10
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@@ -341,6 +341,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_IO.pin[rtcio_num].int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_IO.pin[rtcio_num].edge_wakeup_clr = 1;
}
/**
* Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/esp32c61/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h
+10
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@@ -334,6 +334,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_GPIO.pinn[rtcio_num].pinn_int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_GPIO.pinn[rtcio_num].pinn_edge_wakeup_clr = 1;
}
/**
* @brief Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/esp32h4/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h
+10
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@@ -334,6 +334,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_GPIO.pinn[rtcio_num].pinn_int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_GPIO.pinn[rtcio_num].pinn_edge_wakeup_clr = 1;
}
/**
* @brief Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/esp32p4/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h
+10
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@@ -404,6 +404,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_GPIO.pin[rtcio_num].int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_GPIO.pin[rtcio_num].edge_wakeup_clr = 1;
}
/**
* Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/esp32s31/include/hal/rtc_gpio_caps.h
-2
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@@ -7,5 +7,3 @@
#pragma once
#define RTC_GPIO_CAPS_GET(_attr) _RTC_GPIO_ ## _attr
#define _RTC_GPIO_EDGE_WAKEUP_SUPPORTED 1
components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h
+10
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@@ -333,6 +333,16 @@ static inline void rtcio_ll_wakeup_disable(int rtcio_num)
LP_GPIO.pinn[rtcio_num].pinn_int_type = 0;
}
/**
* Clear edge-wakeup latch.
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
*/
static inline void rtcio_ll_clear_edge_wakeup_latch(int rtcio_num)
{
LP_GPIO.pinn[rtcio_num].pinn_edge_wakeup_clr = 1;
}
/**
* @brief Enable interrupt function and set interrupt type
*
components/esp_hal_gpio/include/hal/rtc_io_hal.h
+14
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@@ -320,6 +320,20 @@ void rtcio_hal_isolate(int rtcio_num);
#define rtc_hal_gpio_get_wakeup_status() rtcio_hal_get_interrupt_status()
#define rtc_hal_gpio_clear_wakeup_status() rtcio_hal_clear_interrupt_status()
#if SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
/**
* @brief Clear the latched edge-wakeup state for a GPIO that is enabled for
* peripheral-powerdown-sleep wakeup in edge mode.
*
* Must be called before entering sleep on every pin configured for posedge/negedge/anyedge
* wakeup, otherwise a stale latched edge would immediately wake the chip.
*
* @param hal Context of the HAL layer (unused, kept for API symmetry).
* @param gpio_num GPIO number.
*/
#define gpio_hal_clear_hp_periph_pd_sleep_edge_wakeup_latch(hal, gpio_num) rtcio_ll_clear_edge_wakeup_latch(rtc_io_num_map[gpio_num])
#endif //SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
/**
* @brief Get the status of whether an IO is used for sleep wake-up.
*
components/esp_hw_support/include/esp_sleep.h
+14 -4
View File
@@ -44,8 +44,15 @@ typedef enum {
#if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
typedef enum {
ESP_GPIO_WAKEUP_GPIO_LOW = 0,
ESP_GPIO_WAKEUP_GPIO_HIGH = 1
ESP_GPIO_WAKEUP_GPIO_HIGH = 1,
#if SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
ESP_GPIO_WAKEUP_GPIO_POSEDGE = 2,
ESP_GPIO_WAKEUP_GPIO_NEGEDGE = 3,
ESP_GPIO_WAKEUP_GPIO_ANYEDGE = 4,
#endif
} esp_sleep_gpio_wake_up_mode_t;
#define WAKEUP_MODE_2_INT_TYPE(mode) ((gpio_int_type_t)((0x32154 >> ((mode) * 4)) & 0xF))
#endif
/**
@@ -482,11 +489,14 @@ __attribute__((deprecated("please use 'esp_sleep_enable_ext1_wakeup_io' and 'esp
* and external resistors may cause interference. BTW, when you use low level to wake up the
* chip, we strongly recommend you to add external resistors (pull-up).
*
* @note The wakeup signal must be held (level mode) or have a pulse width (edge mode)
* of at least 3 RTC slow-clock cycles to be reliably sampled by the wakeup logic.
* The duration of one slow-clock cycle depends on `CONFIG_RTC_CLK_SRC` (e.g.
* RC_SLOW @ ~136 kHz ~= 7.4 us/cycle, XTAL32K @ 32.768 kHz ~= 30.5 us/cycle).
*
* @param gpio_pin_mask Bit mask of GPIO numbers which will cause wakeup. Only GPIOs
* which have RTC functionality (pads that powered by VDD3P3_RTC) can be used in this bit map.
* @param mode Select logic function used to determine wakeup condition:
* - ESP_GPIO_WAKEUP_GPIO_LOW: wake up when the gpio turn to low.
* - ESP_GPIO_WAKEUP_GPIO_HIGH: wake up when the gpio turn to high.
* @param mode Wakeup condition, see esp_sleep_gpio_wake_up_mode_t.
* @return
* - ESP_OK on success
* - ESP_ERR_INVALID_ARG if the mask contains any invalid wakeup pin or wakeup mode is invalid
components/esp_hw_support/sleep_modes.c
+26 -15
View File
@@ -301,7 +301,7 @@ typedef struct {
#endif
#if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
uint64_t gpio_wakeup_mask;
uint64_t gpio_trigger_mode;
uint8_t gpio_trigger_mode[SOC_GPIO_PIN_COUNT];
#endif
uint32_t sleep_time_adjustment;
uint32_t ccount_ticks_record;
@@ -315,7 +315,6 @@ typedef struct {
bool overhead_out_need_remeasure;
} sleep_config_t;
#if CONFIG_ESP_SLEEP_DEBUG
static esp_sleep_context_t *s_sleep_ctx = NULL;
@@ -1782,7 +1781,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) {
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
s_config.gpio_wakeup_mask = 0;
s_config.gpio_trigger_mode = 0;
memset(s_config.gpio_trigger_mode, 0, sizeof(s_config.gpio_trigger_mode));
#endif
s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN;
} else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART0, RTC_UART0_TRIG_EN)) {
@@ -2260,18 +2259,28 @@ static void esp_sleep_gpio_wakeup_prepare_on_hp_periph_powerdown(void)
int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
rtcio_ll_enable_io_clock(true);
#endif
__attribute__ ((unused)) gpio_int_type_t intr_type = (gpio_int_type_t)s_config.gpio_trigger_mode[gpio_idx];
#if CONFIG_ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS
if (GPIO_IS_VALID_OUTPUT_GPIO(gpio_idx)) {
if (s_config.gpio_trigger_mode & BIT(gpio_idx)) {
if (intr_type == GPIO_INTR_LOW_LEVEL || intr_type == GPIO_INTR_NEGEDGE) {
gpio_pullup_en(gpio_idx);
gpio_pulldown_dis(gpio_idx);
} else if (intr_type == GPIO_INTR_HIGH_LEVEL || intr_type == GPIO_INTR_POSEDGE) {
gpio_pullup_dis(gpio_idx);
gpio_pulldown_en(gpio_idx);
} else {
gpio_pullup_en(gpio_idx);
gpio_pullup_dis(gpio_idx);
gpio_pulldown_dis(gpio_idx);
}
} else {
ESP_EARLY_LOGE(TAG, "GPIO%d not support internal PU/PD", gpio_idx);
}
#endif
#if SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
/* Clear any pending edge-wakeup latch so a stale event does not immediately re-wake the chip. */
if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) {
gpio_hal_clear_hp_periph_pd_sleep_edge_wakeup_latch(NULL, gpio_idx);
}
#endif
ESP_ERROR_CHECK(gpio_hold_en(gpio_idx));
valid_wake_io_mask &= valid_wake_io_mask - 1;
@@ -2282,14 +2291,20 @@ static void esp_sleep_gpio_wakeup_prepare_on_hp_periph_powerdown(void)
esp_err_t esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown(uint64_t gpio_pin_mask, esp_sleep_gpio_wake_up_mode_t mode)
{
if (mode > ESP_GPIO_WAKEUP_GPIO_HIGH) {
ESP_LOGE(TAG, "invalid mode");
return ESP_ERR_INVALID_ARG;
}
if (gpio_pin_mask == 0) {
return ESP_ERR_INVALID_ARG;
}
gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL);
const gpio_int_type_t intr_type = WAKEUP_MODE_2_INT_TYPE(mode);
if (intr_type == GPIO_INTR_DISABLE || intr_type > GPIO_INTR_HIGH_LEVEL) {
ESP_LOGE(TAG, "invalid mode");
return ESP_ERR_INVALID_ARG;
}
#if !SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
if (intr_type != GPIO_INTR_LOW_LEVEL && intr_type != GPIO_INTR_HIGH_LEVEL) {
ESP_LOGE(TAG, "invalid mode");
return ESP_ERR_INVALID_ARG;
}
#endif
esp_err_t err = ESP_OK;
uint64_t invalid_io_mask = gpio_pin_mask & ~SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK;
@@ -2306,11 +2321,7 @@ esp_err_t esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown(uint64_t gpio_pin_
err = gpio_wakeup_enable_on_hp_periph_powerdown_sleep(gpio_idx, intr_type);
if (err != ESP_OK) return err;
s_config.gpio_wakeup_mask |= BIT64(gpio_idx);
if (mode == ESP_GPIO_WAKEUP_GPIO_HIGH) {
s_config.gpio_trigger_mode |= BIT64(gpio_idx);
} else {
s_config.gpio_trigger_mode &= ~BIT64(gpio_idx);
}
s_config.gpio_trigger_mode[gpio_idx] = (uint8_t)intr_type;
gpio_pin_mask &= gpio_pin_mask - 1;
}
s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
components/esp_hw_support/test_apps/.build-test-rules.yml
+1 -1
View File
@@ -114,6 +114,6 @@ components/esp_hw_support/test_apps/wakeup_tests:
- esp_hw_support
- soc
disable_test:
- if: IDF_TARGET in ["esp32h21", "esp32h4"]
- if: IDF_TARGET in ["esp32h21"]
temporary: true
reason: lack of runners
components/esp_hw_support/test_apps/wakeup_tests/main/src/io_wakeup_cmd.c
+22 -16
View File
@@ -8,6 +8,7 @@
#include "unity_test_utils.h"
#include "test_utils.h"
#include "esp_sleep.h"
#include "soc/soc_caps.h"
#include "driver/gpio.h"
#include "hal/gpio_ll.h"
#include "esp_console.h"
@@ -84,7 +85,7 @@ static struct {
static int process_ext1_wakeup(int argc, char **argv)
{
int nerrors = arg_parse(argc, argv, (void **) &ext1_wakeup_args);
int io_wakeup_num = 0, io_wakeup_level = 0;
int io_wakeup_num = 0, io_wakeup_type = 0;
if (nerrors != 0) {
arg_print_errors(stderr, ext1_wakeup_args.end, argv[0]);
return 1;
@@ -100,21 +101,21 @@ static int process_ext1_wakeup(int argc, char **argv)
if (ext1_wakeup_args.mode->count) {
if (ext1_wakeup_args.mode->count == 1) {
io_wakeup_level = ext1_wakeup_args.mode->ival[0];
io_wakeup_type = ext1_wakeup_args.mode->ival[0];
} else {
ESP_LOGE(TAG, "no valid arguments");
return 1;
}
}
ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
ESP_LOGI(TAG, "io_wakeup_type = %d\n", io_wakeup_type);
if (ext1_wakeup_args.disable->count) {
ESP_ERROR_CHECK(esp_sleep_disable_ext1_wakeup_io(1ULL << io_wakeup_num));
} else {
#if CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_level == 0 ? ESP_EXT1_WAKEUP_ALL_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_type == 0 ? ESP_EXT1_WAKEUP_ALL_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
#else
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_level == 0 ? ESP_EXT1_WAKEUP_ANY_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
ESP_ERROR_CHECK(esp_sleep_enable_ext1_wakeup_io(1ULL << io_wakeup_num, io_wakeup_type == 0 ? ESP_EXT1_WAKEUP_ANY_LOW : ESP_EXT1_WAKEUP_ANY_HIGH));
#endif
}
return 0;
@@ -151,7 +152,7 @@ static struct {
static int process_rtcio_wakeup(int argc, char **argv)
{
int nerrors = arg_parse(argc, argv, (void **) &rtcio_wakeup_args);
int io_wakeup_num = 0, io_wakeup_level = 0;
int io_wakeup_num = 0, io_wakeup_type = 0;
if (nerrors != 0) {
arg_print_errors(stderr, rtcio_wakeup_args.end, argv[0]);
return 1;
@@ -167,13 +168,13 @@ static int process_rtcio_wakeup(int argc, char **argv)
if (rtcio_wakeup_args.level->count) {
if (rtcio_wakeup_args.level->count == 1) {
io_wakeup_level = rtcio_wakeup_args.level->ival[0];
io_wakeup_type = rtcio_wakeup_args.level->ival[0];
} else {
ESP_LOGE(TAG, "no valid arguments");
return 1;
}
}
ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
ESP_LOGI(TAG, "io_wakeup_type = %d\n", io_wakeup_type);
if (rtcio_wakeup_args.disable->count) {
ESP_ERROR_CHECK(gpio_wakeup_disable_on_hp_periph_powerdown_sleep(io_wakeup_num));
@@ -187,8 +188,8 @@ static int process_rtcio_wakeup(int argc, char **argv)
};
ESP_ERROR_CHECK(gpio_config(&config));
/* Enable wake up from GPIO */
ESP_ERROR_CHECK(esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown(BIT64(io_wakeup_num), io_wakeup_level));
esp_sleep_gpio_wake_up_mode_t mode = (esp_sleep_gpio_wake_up_mode_t)io_wakeup_type;
ESP_ERROR_CHECK(esp_sleep_enable_gpio_wakeup_on_hp_periph_powerdown(BIT64(io_wakeup_num), mode));
}
return 0;
@@ -199,7 +200,12 @@ static void register_rtcio_wakeup(void)
rtcio_wakeup_args.pin =
arg_int0("p", "pin", "<pin>", "configure the rtcio wakeup pin num");
rtcio_wakeup_args.level =
arg_int0("l", "level", "<level>", "configure the rtcio wakeup level");
arg_int0("l", "level", "<mode>",
"esp_sleep_gpio_wake_up_mode_t: 0=LOW, 1=HIGH"
#if SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
", 2=POSEDGE, 3=NEGEDGE, 4=ANYEDGE"
#endif
);
rtcio_wakeup_args.disable =
arg_lit0("d", "disable", "disable the rtcio wakeup on certain pin");
rtcio_wakeup_args.end = arg_end(4);
@@ -225,7 +231,7 @@ static struct {
static int process_gpio_wakeup(int argc, char **argv)
{
int nerrors = arg_parse(argc, argv, (void **) &gpio_wakeup_args);
int io_wakeup_num = 0, io_wakeup_level = 0;
int io_wakeup_num = 0, io_wakeup_type = 0;
if (nerrors != 0) {
arg_print_errors(stderr, gpio_wakeup_args.end, argv[0]);
return 1;
@@ -241,13 +247,13 @@ static int process_gpio_wakeup(int argc, char **argv)
if (gpio_wakeup_args.level->count) {
if (gpio_wakeup_args.level->count == 1) {
io_wakeup_level = gpio_wakeup_args.level->ival[0];
io_wakeup_type = gpio_wakeup_args.level->ival[0];
} else {
ESP_LOGE(TAG, "no valid arguments");
return 1;
}
}
ESP_LOGI(TAG, "io_wakeup_level = %d\n", io_wakeup_level);
ESP_LOGI(TAG, "io_wakeup_type = %d\n", io_wakeup_type);
if (gpio_wakeup_args.disable->count) {
ESP_ERROR_CHECK(gpio_wakeup_disable(io_wakeup_num));
@@ -258,12 +264,12 @@ static int process_gpio_wakeup(int argc, char **argv)
.mode = GPIO_MODE_INPUT,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
.intr_type = (io_wakeup_level == 0) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL
.intr_type = (io_wakeup_type == 0) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL
};
ESP_ERROR_CHECK(gpio_config(&config));
/* Enable wake up from GPIO */
ESP_ERROR_CHECK(gpio_wakeup_enable(io_wakeup_num, io_wakeup_level == 0 ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL));
ESP_ERROR_CHECK(gpio_wakeup_enable(io_wakeup_num, io_wakeup_type == 0 ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL));
ESP_ERROR_CHECK(esp_sleep_enable_gpio_wakeup());
}
components/esp_hw_support/test_apps/wakeup_tests/pytest_wakeup_tests.py
+31 -14
View File
@@ -24,8 +24,14 @@ available_gpio_nums = {
+ [28, 29, 30, 31, 32, 33, 36, 49, 50, 51, 52, 53, 54],
'esp32c5': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 23, 24, 25, 26],
'esp32c61': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 22, 23, 24, 25, 26, 27, 28, 29],
'esp32h4': [0, 1, 2, 3, 4, 5, 15, 16, 18, 19, 20, 21, 22, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 38, 39],
'esp32s31': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]
+ [42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57],
}
# Matches SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED in soc_caps.h (HP-periph PD GPIO wakeup edge)
RTC_GPIO_EDGE_HP_PD_TARGETS = frozenset({'esp32c5', 'esp32c6', 'esp32c61', 'esp32p4', 'esp32h4'})
available_rtcio_nums = {
'esp32': [36, 37, 38, 39, 34, 35, 25, 26, 33, 32, 4, 0, 2, 15, 13, 12, 14, 27],
'esp32s2': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21],
@@ -37,6 +43,8 @@ available_rtcio_nums = {
'esp32p4': [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
'esp32c5': [0, 1, 2, 3, 4, 5, 6],
'esp32c61': [0, 1, 2, 3, 4, 5, 6],
'esp32h4': [0, 1, 2, 3, 4, 5],
'esp32s31': [0, 1, 2, 3, 4, 5, 6, 7],
}
@@ -48,7 +56,6 @@ available_rtcio_nums = {
soc_filtered_targets('SOC_PM_SUPPORT_EXT1_WAKEUP == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1'),
indirect=['target'],
)
@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='lack of multi-device runners') # TODO: IDFCI-10702
def test_ext1_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee = dut[0]
waker = dut[1]
@@ -67,7 +74,7 @@ def test_ext1_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee.expect('io_wakeup_test>', timeout=10)
wakee.write(f'ext1 -p {gpio_num} -m {wakeup_level}')
wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
wakee.expect(f'io_wakeup_type = {wakeup_level}', timeout=10)
waker.expect('io_wakeup_test>', timeout=10)
sleep_level = 1 - wakeup_level
@@ -100,7 +107,6 @@ def test_ext1_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
@pytest.mark.parametrize('count', [2], indirect=True)
@pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
@idf_parametrize('target', soc_filtered_targets('SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='lack of multi-device runners') # TODO: IDFCI-10702
def test_rtcio_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee = dut[0]
waker = dut[1]
@@ -109,7 +115,21 @@ def test_rtcio_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
gpio_nums = available_gpio_nums.get(chip_type, [])
rtcio_nums = available_rtcio_nums.get(chip_type, [])
for wakeup_level in [0, 1]:
# Modes: 0=LOW, 1=HIGH, 2=POSEDGE, 3=NEGEDGE, 4=ANYEDGE
# Tuple: (esp_sleep_gpio_wake_up_mode_t as int, waker_level_before_sleep, waker_level_to_wake)
dslp_io_wakeup_cases = [
(0, 1, 0), # low level: hold high, then pull low
(1, 0, 1), # high level: hold low, then drive high
]
if chip_type in RTC_GPIO_EDGE_HP_PD_TARGETS:
dslp_io_wakeup_cases += [
(2, 0, 1), # posedge: low then rising edge
(3, 1, 0), # negedge: high then falling edge
(4, 0, 1), # anyedge: rising edge from low
(4, 1, 0), # anyedge: falling edge from high
]
for wakeup_mode, prep_level, wake_level in dslp_io_wakeup_cases:
for gpio_num in rtcio_nums:
if gpio_num not in gpio_nums:
continue
@@ -117,23 +137,22 @@ def test_rtcio_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee.write('\r\n')
sleep(0.1)
wakee.expect('io_wakeup_test>', timeout=10)
wakee.write(f'rtcio -p {gpio_num} -l {wakeup_level}')
wakee.write(f'rtcio -p {gpio_num} -l {wakeup_mode}')
wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
wakee.expect(f'io_wakeup_type = {wakeup_mode}', timeout=10)
waker.expect('io_wakeup_test>', timeout=10)
sleep_level = 1 - wakeup_level
waker.write(f'gpio_control -p {gpio_num} -l {sleep_level}')
waker.write(f'gpio_control -p {gpio_num} -l {prep_level}')
waker.expect(f'io_num = {gpio_num}', timeout=10)
waker.expect(f'io_level = {sleep_level}', timeout=10)
waker.expect(f'io_level = {prep_level}', timeout=10)
wakee.write('sleep -m 1')
wakee.expect('enter deep sleep', timeout=10)
sleep(2)
waker.write(f'gpio_control -p {gpio_num} -l {wakeup_level}')
waker.write(f'gpio_control -p {gpio_num} -l {wake_level}')
waker.expect(f'io_num = {gpio_num}', timeout=10)
waker.expect(f'io_level = {wakeup_level}', timeout=10)
waker.expect(f'io_level = {wake_level}', timeout=10)
wakee.expect('io_wakeup_test>', timeout=10)
wakee.write('cause')
@@ -146,8 +165,6 @@ def test_rtcio_deepsleep(dut: tuple[IdfDut, IdfDut]) -> None:
@pytest.mark.parametrize('count', [2], indirect=True)
@pytest.mark.parametrize('config', TEST_CONFIGS, indirect=True)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='bringup on this module is not done')
@pytest.mark.temp_skip_ci(targets=['esp32h4'], reason='lack of multi-device runners') # TODO: IDFCI-10702
def test_gpio_wakeup_enable_lightsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee = dut[0]
waker = dut[1]
@@ -161,7 +178,7 @@ def test_gpio_wakeup_enable_lightsleep(dut: tuple[IdfDut, IdfDut]) -> None:
wakee.expect('io_wakeup_test>', timeout=10)
wakee.write(f'gpio -p {gpio_num} -l {wakeup_level}')
wakee.expect(f'io_wakeup_num = {gpio_num}', timeout=10)
wakee.expect(f'io_wakeup_level = {wakeup_level}', timeout=10)
wakee.expect(f'io_wakeup_type = {wakeup_level}', timeout=10)
waker.expect('io_wakeup_test>', timeout=10)
sleep_level = 1 - wakeup_level
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -579,6 +579,10 @@ config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
config SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
View File
@@ -227,6 +227,7 @@
// GPIO0~7 on ESP32C5 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED (1)
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -499,6 +499,10 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
components/soc/esp32c6/include/soc/soc_caps.h
+1
View File
@@ -202,6 +202,7 @@
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -463,6 +463,10 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
bool
default y
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x3FFFFF80
components/soc/esp32c61/include/soc/soc_caps.h
+1
View File
@@ -192,6 +192,7 @@
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED (1)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -507,6 +507,10 @@ config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
bool
default y
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+1
View File
@@ -227,6 +227,7 @@
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED (1)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -703,6 +703,10 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED
bool
default y
config SOC_GPIO_VALID_GPIO_MASK
hex
default 0x007FFFFFFFFFFFFF
components/soc/esp32p4/include/soc/soc_caps.h
+1
View File
@@ -263,6 +263,7 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_RTC_GPIO_EDGE_WAKEUP_SUPPORTED (1)
#define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK