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refactor(i2s): clean up i2s soc caps

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This commit is contained in:
laokaiyao
2025-10-01 21:51:58 +08:00
parent 31602cbe66
commit 91a6387005
64 changed files with 172 additions and 397 deletions
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components/soc/esp32/i2s_periph.c
+1 -1
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@@ -10,7 +10,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = -1, // Unavailable
.mck_in_sig = -1, // Unavailable
components/soc/esp32/include/soc/Kconfig.soc_caps.in
-28
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@@ -383,10 +383,6 @@ config SOC_I2C_STOP_INDEPENDENT
bool
default y
config SOC_I2S_NUM
int
default 2
config SOC_I2S_HW_VERSION_1
bool
default y
@@ -395,10 +391,6 @@ config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PDM
bool
default y
@@ -427,30 +419,10 @@ config SOC_I2S_PDM_MAX_RX_LINES
int
default 1
config SOC_I2S_SUPPORTS_ADC_DAC
bool
default y
config SOC_I2S_SUPPORTS_ADC
bool
default y
config SOC_I2S_SUPPORTS_LCD_CAMERA
bool
default y
config SOC_I2S_MAX_DATA_WIDTH
int
default 24
config SOC_I2S_TRANS_SIZE_ALIGN_WORD
bool
default y
config SOC_I2S_LCD_I80_VARIANT
bool
default y
config SOC_LCD_I80_SUPPORTED
bool
default y
components/soc/esp32/include/soc/soc_caps.h
-8
View File
@@ -217,10 +217,8 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32 has 2 I2S
#define SOC_I2S_NUM (2U)
#define SOC_I2S_HW_VERSION_1 (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter
@@ -228,13 +226,7 @@
#define SOC_I2S_SUPPORTS_PDM2PCM (1) // Support to input PDM format but read PCM format data with the help of PDM to PCM filter
#define SOC_I2S_PDM_MAX_TX_LINES (1U)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_ADC_DAC (1)
#define SOC_I2S_SUPPORTS_ADC (1)
#define SOC_I2S_SUPPORTS_LCD_CAMERA (1)
#define SOC_I2S_MAX_DATA_WIDTH (24)
#define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word
#define SOC_I2S_LCD_I80_VARIANT (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing
/*-------------------------- LCD CAPS ----------------------------------------*/
/* Notes: On esp32, LCD intel 8080 timing is generated by I2S peripheral */
components/soc/esp32/include/soc/soc_caps_full.h
+8
View File
@@ -29,3 +29,11 @@
#define _SOC_CAPS_PCNT_UNITS_PER_INST 8 // Number of units in each PCNT instance
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 2 // Number of I2S instances
#define _SOC_CAPS_I2S_MAX_DATA_WIDTH 24 // Maximum data line width of I2S
#define _SOC_CAPS_I2S_TRANS_SIZE_ALIGN_WORD 1 // I2S DMA transfer size must be aligned to word
#define _SOC_CAPS_I2S_SUPPORT_ADC_DAC 1 // I2S supports to connect to ADC / DAC converters
components/soc/esp32c3/i2s_periph.c
+1 -1
View File
@@ -10,7 +10,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -479,22 +479,10 @@ config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
-3
View File
@@ -213,10 +213,7 @@
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
components/soc/esp32c3/include/soc/soc_caps_full.h
+5
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@@ -27,3 +27,8 @@
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32c5/i2s_periph.c
+2 -2
View File
@@ -11,7 +11,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
@@ -64,7 +64,7 @@ static const uint32_t i2s_regs_map[4] = {0x12360f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-24
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@@ -707,10 +707,6 @@ config SOC_LP_I2C_FIFO_LEN
int
default 16
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -719,18 +715,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F240M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
@@ -767,14 +751,6 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-6
View File
@@ -294,12 +294,8 @@
#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PLL_F240M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
@@ -309,8 +305,6 @@
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32c5/include/soc/soc_caps_full.h
+5
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@@ -37,3 +37,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32c6/i2s_periph.c
+2 -2
View File
@@ -11,7 +11,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
@@ -64,7 +64,7 @@ static const uint32_t i2s_regs_map[4] = {0x12330f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-16
View File
@@ -635,10 +635,6 @@ config SOC_LP_I2C_FIFO_LEN
int
default 16
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -647,14 +643,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
@@ -687,10 +675,6 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
-4
View File
@@ -271,11 +271,8 @@
#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
@@ -284,7 +281,6 @@
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32c6/include/soc/soc_caps_full.h
+5
View File
@@ -37,3 +37,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32c61/i2s_periph.c
+2 -2
View File
@@ -11,7 +11,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
@@ -64,7 +64,7 @@ static const uint32_t i2s_regs_map[4] = {0x12360f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-24
View File
@@ -571,10 +571,6 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -583,18 +579,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F120M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
@@ -631,14 +615,6 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
-6
View File
@@ -242,12 +242,8 @@
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
// /*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PLL_F120M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
@@ -257,8 +253,6 @@
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32c61/include/soc/soc_caps_full.h
+5
View File
@@ -27,3 +27,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*--------------------------- I2S CAPS ----------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h2/i2s_periph.c
+2 -2
View File
@@ -11,7 +11,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
@@ -63,7 +63,7 @@ static const uint32_t i2s_regs_map[4] = {0x12330f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-24
View File
@@ -639,10 +639,6 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -651,18 +647,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F96M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F64M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
@@ -695,14 +679,6 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
-6
View File
@@ -289,12 +289,8 @@
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
#define SOC_I2S_SUPPORTS_PLL_F64M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
@@ -303,8 +299,6 @@
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32h2/include/soc/soc_caps_full.h
+5
View File
@@ -37,3 +37,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h21/include/soc/soc_caps.h
-5
View File
@@ -270,18 +270,13 @@
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// // #define SOC_I2S_SUPPORTS_ETM (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F96M (1)
// #define SOC_I2S_SUPPORTS_PLL_F64M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
// #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32h21/include/soc/soc_caps_full.h
+5
View File
@@ -33,3 +33,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
// #define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
// #define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32h4/i2s_periph.c
+2 -2
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@@ -11,7 +11,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S_MCLK_OUT_IDX,
.mck_in_sig = I2S_MCLK_IN_IDX,
@@ -68,7 +68,7 @@ static const uint32_t i2s_regs_map[4] = {0xf191b079, 0x0, 0x0, 0x0};
};
static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
-24
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@@ -419,10 +419,6 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -431,18 +427,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F96M
bool
default y
config SOC_I2S_SUPPORTS_PLL_F64M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
@@ -483,14 +467,6 @@ config SOC_I2S_SUPPORTS_TDM
bool
default y
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
-7
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@@ -268,12 +268,8 @@
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
#define SOC_I2S_SUPPORTS_PLL_F64M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
@@ -284,9 +280,6 @@
#define SOC_I2S_PDM_MAX_TX_LINES (2)
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
components/soc/esp32h4/include/soc/soc_caps_full.h
+5
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@@ -33,3 +33,8 @@
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
components/soc/esp32p4/i2s_periph.c
+2 -2
View File
@@ -12,7 +12,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.mck_out_sig = I2S0_MCLK_PAD_OUT_IDX,
.mck_in_sig = I2S0_MCLK_PAD_IN_IDX,
@@ -143,7 +143,7 @@ static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION
static const regdma_entries_config_t i2s1_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(1);
static const regdma_entries_config_t i2s2_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(2);
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)] = {
[0] = {
.retention_module = SLEEP_RETENTION_MODULE_I2S0,
.entry_array = i2s0_regs_retention,
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-16
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@@ -839,10 +839,6 @@ config SOC_LP_I2C_FIFO_LEN
int
default 16
config SOC_I2S_NUM
int
default 3
config SOC_I2S_HW_VERSION_2
bool
default y
@@ -851,10 +847,6 @@ config SOC_I2S_SUPPORTS_ETM
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_APLL
bool
default y
@@ -903,14 +895,6 @@ config SOC_I2S_PDM_MAX_RX_LINES
int
default 4
config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LP_I2S_NUM
int
default 1
components/soc/esp32p4/include/soc/soc_caps.h
-4
View File
@@ -330,10 +330,8 @@
#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (3U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_ETM (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
@@ -346,8 +344,6 @@
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LP_I2S CAPS -------------------------------------*/
#define SOC_LP_I2S_NUM (1U)
components/soc/esp32p4/include/soc/soc_caps_full.h
+5
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@@ -40,3 +40,8 @@
/*--------------------------- MIPI DSI -------------------------------------------*/
#define _SOC_CAPS_MIPI_DSI_INST_NUM 1 // Number of MIPI DSI instances
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 3 // Number of I2S instances
components/soc/esp32s2/i2s_periph.c
+1 -1
View File
@@ -10,7 +10,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = CLK_I2S_MUX_IDX,
.mck_in_sig = -1, // Unavailable
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
-32
View File
@@ -451,10 +451,6 @@ config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_I2S_NUM
int
default 1
config SOC_I2S_HW_VERSION_1
bool
default y
@@ -463,38 +459,10 @@ config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_DMA_EQUAL
bool
default y
config SOC_I2S_SUPPORTS_LCD_CAMERA
bool
default y
config SOC_I2S_MAX_DATA_WIDTH
int
default 24
config SOC_I2S_APLL_MIN_FREQ
int
default 250000000
config SOC_I2S_APLL_MAX_FREQ
int
default 500000000
config SOC_I2S_APLL_MIN_RATE
int
default 10675
config SOC_I2S_LCD_I80_VARIANT
bool
default y
config SOC_LCD_I80_SUPPORTED
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
-8
View File
@@ -213,17 +213,9 @@
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 has 1 I2S
#define SOC_I2S_NUM (1U)
#define SOC_I2S_HW_VERSION_1 (1)
#define SOC_I2S_SUPPORTS_APLL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_DMA_EQUAL (1)
#define SOC_I2S_SUPPORTS_LCD_CAMERA (1)
#define SOC_I2S_MAX_DATA_WIDTH (24)
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_LCD_I80_VARIANT (1)
/*-------------------------- LCD CAPS ----------------------------------------*/
/* Notes: On esp32-s2, LCD intel 8080 timing is generated by I2S peripheral */
components/soc/esp32s2/include/soc/soc_caps_full.h
+7
View File
@@ -33,3 +33,10 @@
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 1 // Number of I2S instances
#define _SOC_CAPS_I2S_MAX_DATA_WIDTH 24
#define _SOC_CAPS_I2S_SUPPORT_DMA_EQUAL 1
components/soc/esp32s3/i2s_periph.c
+1 -1
View File
@@ -10,7 +10,7 @@
/*
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)] = {
{
.mck_out_sig = I2S0_MCLK_OUT_IDX,
.mck_in_sig = I2S0_MCLK_IN_IDX,
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -543,22 +543,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2S_NUM
int
default 2
config SOC_I2S_HW_VERSION_2
bool
default y
config SOC_I2S_SUPPORTS_XTAL
bool
default y
config SOC_I2S_SUPPORTS_PLL_F160M
bool
default y
config SOC_I2S_SUPPORTS_PCM
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
-3
View File
@@ -229,10 +229,7 @@
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
#define SOC_I2S_NUM (2U)
#define SOC_I2S_HW_VERSION_2 (1)
#define SOC_I2S_SUPPORTS_XTAL (1)
#define SOC_I2S_SUPPORTS_PLL_F160M (1)
#define SOC_I2S_SUPPORTS_PCM (1)
#define SOC_I2S_SUPPORTS_PDM (1)
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
components/soc/esp32s3/include/soc/soc_caps_full.h
+5
View File
@@ -33,3 +33,8 @@
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*------------------------------- I2S ---------------------------------------*/
// helper macros to access module attributes
#define SOC_I2S_ATTR(_attr) SOC_MODULE_ATTR(I2S, _attr)
#define _SOC_CAPS_I2S_INST_NUM 2 // Number of I2S instances
components/soc/include/soc/i2s_periph.h
+10 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,12 +8,13 @@
#include "soc/soc.h"
#include "soc/interrupts.h"
#include "soc/soc_caps.h"
#include "soc/soc_caps_full.h"
#include "soc/regdma.h"
#if SOC_I2S_SUPPORT_SLEEP_RETENTION
#if SOC_HAS(PAU)
#include "soc/retention_periph_defs.h"
#endif
#if SOC_I2S_SUPPORTED
#if SOC_HAS(I2S)
#include "soc/i2s_struct.h"
#include "soc/i2s_reg.h"
#endif
@@ -22,7 +23,7 @@
extern "C" {
#endif
#if SOC_I2S_SUPPORTED
#if SOC_HAS(I2S)
/*
Stores a bunch of per-I2S-peripheral data.
*/
@@ -57,23 +58,22 @@ typedef struct {
const uint8_t irq;
} i2s_signal_conn_t;
extern const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM];
extern const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_ATTR(INST_NUM)];
#if SOC_LP_I2S_SUPPORTED
extern const i2s_signal_conn_t lp_i2s_periph_signal[SOC_LP_I2S_NUM];
#endif
#endif // SOC_I2S_SUPPORTED
#if SOC_I2S_SUPPORT_SLEEP_RETENTION
#if SOC_HAS(PAU)
typedef struct {
const periph_retention_module_t retention_module;
const regdma_entries_config_t *entry_array;
uint32_t array_size;
} i2s_reg_retention_info_t;
extern const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM];
#endif // SOC_I2S_SUPPORT_SLEEP_RETENTION
extern const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_ATTR(INST_NUM)];
#endif // SOC_HAS(PAU)
#endif // SOC_HAS(I2S)
#ifdef __cplusplus
}
components/soc/include/soc/lcd_periph.h
+2 -1
View File
@@ -8,6 +8,7 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/soc_caps_full.h"
#ifdef __cplusplus
extern "C" {
@@ -50,7 +51,7 @@ typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_I2S_MAX_DATA_WIDTH];
const int data_sigs[SOC_MODULE_ATTR(I2S, MAX_DATA_WIDTH)];
const int wr_sig;
} buses[SOC_LCD_I80_BUSES];
} lcd_i2s_signal_conn_t;