diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c
index e71c70f1de0..d0d76c9ac28 100644
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -119,7 +119,9 @@ static adc_ll_digi_convert_mode_t get_convert_mode(adc_digi_convert_mode_t conve
 static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, adc_continuous_clk_src_t clk_src, uint32_t clk_src_freq_hz, uint32_t sample_freq_hz)
 {
 #if !CONFIG_IDF_TARGET_ESP32
-    uint32_t interval = clk_src_freq_hz / (ADC_LL_CLKM_DIV_NUM_DEFAULT + ADC_LL_CLKM_DIV_A_DEFAULT / ADC_LL_CLKM_DIV_B_DEFAULT + 1) / 2 / sample_freq_hz;
+    uint64_t clkm_div_denom = ((uint64_t)(ADC_LL_CLKM_DIV_NUM_DEFAULT + 1) * ADC_LL_CLKM_DIV_B_DEFAULT) + ADC_LL_CLKM_DIV_A_DEFAULT;
+    uint32_t interval = (uint32_t)(((uint64_t)clk_src_freq_hz * ADC_LL_CLKM_DIV_B_DEFAULT) /
+                                   (clkm_div_denom * 2 * sample_freq_hz));
     //set sample interval
     adc_ll_digi_set_trigger_interval(interval);
     //Here we set the clock divider factor to make the digital clock to 5M Hz
diff --git a/components/hal/adc_oneshot_hal.c b/components/hal/adc_oneshot_hal.c
index b9cfdcbe8f8..4beaf4380a1 100644
--- a/components/hal/adc_oneshot_hal.c
+++ b/components/hal/adc_oneshot_hal.c
@@ -64,7 +64,7 @@ void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t chan)
 
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     adc_ll_digi_clk_sel(hal->clk_src);
-    adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT);
+    adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT);
     adc_ll_digi_set_clk_div(ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT);
 #else
 #if SOC_LP_ADC_SUPPORTED
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index 09fbc83d278..9a166b6faf3 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -146,7 +146,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
-    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.sar_clk_div, sar1_clk_div_num, div);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index de6d2148e30..8863682f450 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -56,11 +56,11 @@ extern "C" {
 #define ADC_LL_FSM_START_WAIT_DEFAULT                  (5)
 #define ADC_LL_FSM_STANDBY_WAIT_DEFAULT                (100)
 #define ADC_LL_SAMPLE_CYCLE_DEFAULT                    (2)
-#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT                (2)
+#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT                (1)
 
-#define ADC_LL_CLKM_DIV_NUM_DEFAULT       19
-#define ADC_LL_CLKM_DIV_B_DEFAULT         1
-#define ADC_LL_CLKM_DIV_A_DEFAULT         0
+#define ADC_LL_CLKM_DIV_NUM_DEFAULT       18
+#define ADC_LL_CLKM_DIV_B_DEFAULT         5
+#define ADC_LL_CLKM_DIV_A_DEFAULT         1
 #define ADC_LL_DEFAULT_CONV_LIMIT_EN      0
 #define ADC_LL_DEFAULT_CONV_LIMIT_NUM     255
 
@@ -146,7 +146,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
-    HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.sar_clk_div, sar1_clk_div_num, div);
 }
 
 /**