diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
index a71f8acdb72..f602074bb63 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
@@ -23,6 +23,7 @@
 #include "hal/mspi_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/clk_tree_ll.h"
 #include "esp_private/bootloader_flash_internal.h"
 
 void IRAM_ATTR bootloader_flash_update_id(void)
@@ -46,6 +47,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
 void IRAM_ATTR bootloader_init_mspi_clock(void)
 {
     cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
+    clk_ll_bbpll_enable();
     _mspi_timing_ll_set_flash_core_clock(0, 80);
     _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_BBPLL);
     cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
index 2ab911c88c1..965af764f03 100644
--- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
+++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
@@ -34,7 +34,6 @@
 #include "esp_rom_sys.h"
 #include "soc/regi2c_bias.h"
 #include "hal/regi2c_ctrl.h"
-#include "hal/clk_tree_ll.h"
 #include "hal/psram_ctrlr_ll.h"
 
 ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31");
@@ -61,11 +60,11 @@ static inline void bootloader_hardware_init(void)
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10);
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 
-    /* Disable MPLL by default, during mmu_hal_init, a valid clock source is required for the PSRAM,
-       so before shutting down mpll, the PSRAM clock source should be selected to an always-on source. */
+    /* During mmu_hal_init, a valid clock source is required for the PSRAM,
+       so before shutting down MPLL in rtc_clk_init, the PSRAM clock source
+       should be selected to an always-on source. */
     _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL);
     _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL);
-    clk_ll_mpll_disable();
 }
 
 void bootloader_enable_cpu_reset_info(void)
diff --git a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h
index 7d0dadb89f0..44c5ee342e3 100644
--- a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h
@@ -88,6 +88,10 @@ typedef struct {
     uint32_t slow_clk_dcap : 8;                //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency)
     uint32_t clk_8m_dfreq : 8;                 //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency)
     uint32_t rc32k_dfreq : 10;                 //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency)
+    uint32_t disable_apll : 1;                 //!< Whether to disable APLL  in rtc_clk_init
+    uint32_t disable_mpll : 1;                 //!< Whether to disable MPLL  in rtc_clk_init
+    uint32_t disable_cpll : 1;                 //!< Whether to disable CPLL  in rtc_clk_init
+    uint32_t disable_bbpll : 1;                //!< Whether to disable BBPLL in rtc_clk_init
 } rtc_clk_config_t;
 
 /**
@@ -103,6 +107,10 @@ typedef struct {
     .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
     .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
     .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
+    .disable_apll = 1, \
+    .disable_mpll = 1, \
+    .disable_cpll = 0, \
+    .disable_bbpll = 1, \
 }
 
 /**
diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk_init.c b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c
index 0e14f89fbf0..75ffc533bbb 100644
--- a/components/esp_hw_support/port/esp32s31/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c
@@ -8,6 +8,7 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <stdlib.h>
+#include "sdkconfig.h"
 #include "esp32s31/rom/ets_sys.h"
 #include "esp32s31/rom/rtc.h"
 #include "soc/rtc.h"
@@ -27,6 +28,25 @@
 
 ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init");
 
+static inline void rtc_clk_pll_disable(rtc_clk_config_t cfg)
+{
+    if (cfg.disable_apll) {
+        clk_ll_apll_disable();
+    }
+    if (cfg.disable_mpll) {
+        clk_ll_mpll_disable();
+    }
+    if (cfg.disable_cpll) {
+        clk_ll_cpll_disable();
+    }
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+    // USB-Serial-JTAG depends on bbpll480M, bypass disable bbpll if USB console is used.
+    if (cfg.disable_bbpll) {
+        clk_ll_bbpll_disable();
+    }
+#endif
+}
+
 void rtc_clk_init(rtc_clk_config_t cfg)
 {
     rtc_cpu_freq_config_t old_config, new_config;
@@ -50,6 +70,9 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
     // No need to wait UART0 TX idle since its default clock source is XTAL, should not be affected by system clock configuration
 
+    /* Disable PLLs to save power, the PLLs will be enabled by the user in application code */
+    rtc_clk_pll_disable(cfg);
+
     /* Set CPU frequency */
     rtc_clk_cpu_freq_get_config(&old_config);
     uint32_t freq_before = old_config.freq_mhz;