feat(esp_system): add CPU lockup debug support for esp32h4 and esp32s31

This commit is contained in:
Marius Vikhammer
2026-04-22 11:11:02 +08:00
parent 38e2cacc27
commit 8e2b416c38
38 changed files with 533 additions and 246 deletions
@@ -48,7 +48,7 @@
ESP_LOG_ATTR_TAG(TAG, "boot.esp32s3");
#if SOC_RTC_WDT_SUPPORTED
static void wdt_reset_cpu0_info_enable(void)
void bootloader_enable_cpu_reset_info(void)
{
REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
@@ -56,7 +56,7 @@ static void wdt_reset_cpu0_info_enable(void)
REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
}
static void wdt_reset_info_dump(int cpu)
void bootloader_dump_wdt_reset_info(int cpu)
{
uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
@@ -98,31 +98,21 @@ static void wdt_reset_info_dump(int cpu)
ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
}
static void bootloader_check_wdt_reset(void)
bool bootloader_check_if_wdt_reset(int cpu, soc_reset_reason_t rst_reason)
{
int wdt_rst = 0;
soc_reset_reason_t rst_reas[2];
rst_reas[0] = esp_rom_get_reset_reason(0);
rst_reas[1] = esp_rom_get_reset_reason(1);
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
if (cpu == 0 && (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 ||
rst_reason == RESET_REASON_CORE_MWDT1 || rst_reason == RESET_REASON_CPU0_MWDT0 ||
rst_reason == RESET_REASON_CPU0_RTC_WDT)) {
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
wdt_rst = 1;
return true;
}
if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
if (cpu == 1 && (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 ||
rst_reason == RESET_REASON_CORE_MWDT1 || rst_reason == RESET_REASON_CPU1_MWDT1 ||
rst_reason == RESET_REASON_CPU1_RTC_WDT)) {
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
wdt_rst = 1;
return true;
}
if (wdt_rst) {
// if reset by WDT dump info from trace port
wdt_reset_info_dump(0);
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
wdt_reset_info_dump(1);
#endif
}
wdt_reset_cpu0_info_enable();
return false;
}
static void bootloader_super_wdt_auto_feed(void)
@@ -208,10 +198,8 @@ esp_err_t bootloader_init(void)
}
#endif // !CONFIG_APP_BUILD_TYPE_RAM
#if SOC_RTC_WDT_SUPPORTED
// check whether a WDT reset happened
bootloader_check_wdt_reset();
#endif
// check reset reason and dump diagnostic info
bootloader_check_reset();
#if SOC_RTC_WDT_SUPPORTED || SOC_WDT_SUPPORTED
// config WDT
bootloader_config_wdt();