mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 10:40:47 +03:00
feat(esp_system): add CPU lockup debug support for esp32h4 and esp32s31
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@@ -48,7 +48,7 @@
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ESP_LOG_ATTR_TAG(TAG, "boot.esp32s3");
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#if SOC_RTC_WDT_SUPPORTED
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static void wdt_reset_cpu0_info_enable(void)
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void bootloader_enable_cpu_reset_info(void)
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{
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REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
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REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
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@@ -56,7 +56,7 @@ static void wdt_reset_cpu0_info_enable(void)
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
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}
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static void wdt_reset_info_dump(int cpu)
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void bootloader_dump_wdt_reset_info(int cpu)
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{
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uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
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lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
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@@ -98,31 +98,21 @@ static void wdt_reset_info_dump(int cpu)
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ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08"PRIx32, cpu_name, lsdata);
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}
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static void bootloader_check_wdt_reset(void)
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bool bootloader_check_if_wdt_reset(int cpu, soc_reset_reason_t rst_reason)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reas[2];
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rst_reas[0] = esp_rom_get_reset_reason(0);
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rst_reas[1] = esp_rom_get_reset_reason(1);
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if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
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if (cpu == 0 && (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 ||
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rst_reason == RESET_REASON_CORE_MWDT1 || rst_reason == RESET_REASON_CPU0_MWDT0 ||
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rst_reason == RESET_REASON_CPU0_RTC_WDT)) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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return true;
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}
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if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
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rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
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if (cpu == 1 && (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 ||
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rst_reason == RESET_REASON_CORE_MWDT1 || rst_reason == RESET_REASON_CPU1_MWDT1 ||
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rst_reason == RESET_REASON_CPU1_RTC_WDT)) {
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ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
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wdt_rst = 1;
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return true;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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wdt_reset_info_dump(1);
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#endif
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}
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wdt_reset_cpu0_info_enable();
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return false;
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}
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static void bootloader_super_wdt_auto_feed(void)
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@@ -208,10 +198,8 @@ esp_err_t bootloader_init(void)
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}
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#endif // !CONFIG_APP_BUILD_TYPE_RAM
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#if SOC_RTC_WDT_SUPPORTED
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// check whether a WDT reset happened
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bootloader_check_wdt_reset();
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#endif
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// check reset reason and dump diagnostic info
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bootloader_check_reset();
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#if SOC_RTC_WDT_SUPPORTED || SOC_WDT_SUPPORTED
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// config WDT
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bootloader_config_wdt();
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