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https://github.com/espressif/esp-idf.git
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feat(esp_system): add CPU lockup debug support for esp32h4 and esp32s31
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@@ -47,34 +47,29 @@
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ESP_LOG_ATTR_TAG(TAG, "boot.esp32c3");
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#if SOC_RTC_WDT_SUPPORTED
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static void wdt_reset_cpu0_info_enable(void)
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void bootloader_enable_cpu_reset_info(void)
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{
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REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
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REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
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REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
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}
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static void wdt_reset_info_dump(int cpu)
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void bootloader_dump_wdt_reset_info(int cpu)
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{
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(void) cpu;
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// saved PC was already printed by the ROM bootloader.
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// nothing to do here.
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}
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static void bootloader_check_wdt_reset(void)
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bool bootloader_check_if_wdt_reset(int cpu, soc_reset_reason_t rst_reason)
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{
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int wdt_rst = 0;
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soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
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(void) cpu;
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if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 || rst_reason == RESET_REASON_CORE_MWDT1 ||
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rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_MWDT1 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
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ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
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wdt_rst = 1;
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return true;
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}
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if (wdt_rst) {
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// if reset by WDT dump info from trace port
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wdt_reset_info_dump(0);
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}
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wdt_reset_cpu0_info_enable();
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return false;
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}
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static void bootloader_super_wdt_auto_feed(void)
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@@ -185,10 +180,8 @@ esp_err_t bootloader_init(void)
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}
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#endif //#if !CONFIG_APP_BUILD_TYPE_RAM
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#if SOC_RTC_WDT_SUPPORTED
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// check whether a WDT reset happened
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bootloader_check_wdt_reset();
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#endif
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// check reset reason and dump diagnostic info
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bootloader_check_reset();
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#if SOC_RTC_WDT_SUPPORTED || SOC_WDT_SUPPORTED
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// config WDT
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bootloader_config_wdt();
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