mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-01 18:50:34 +03:00
feat(i2s): support i2s & apll on esp32s31
This commit is contained in:
laokaiyao
Chen Chen
@@ -486,7 +486,7 @@ typedef enum {
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
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I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
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I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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I2S_CLK_SRC_XTAL_X2 = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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@@ -452,7 +452,7 @@ typedef enum {
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
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I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
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I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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I2S_CLK_SRC_XTAL_X2 = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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@@ -111,6 +111,10 @@ config SOC_RMT_SUPPORTED
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bool
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default y
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config SOC_I2S_SUPPORTED
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bool
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default y
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config SOC_SDM_SUPPORTED
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bool
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default y
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@@ -911,6 +915,10 @@ config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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config SOC_CLK_APLL_SUPPORTED
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bool
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default y
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config SOC_CLK_MPLL_SUPPORTED
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bool
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default y
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@@ -927,6 +935,10 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
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bool
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default y
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config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
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bool
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default y
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config SOC_RCC_IS_INDEPENDENT
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bool
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default y
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@@ -1198,3 +1210,75 @@ config SOC_BLE_SUBRATE_SUPPORTED
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config SOC_BLE_PERIODIC_ADV_WITH_RESPONSE
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bool
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default y
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config SOC_I2S_NUM
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int
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default 2
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config SOC_I2S_HW_VERSION_2
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bool
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default y
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config SOC_I2S_SUPPORTS_ETM
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bool
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default y
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config SOC_I2S_SUPPORTS_APLL
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bool
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default y
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config SOC_I2S_SUPPORTS_RTC_FAST
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bool
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default y
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config SOC_I2S_SUPPORTS_EXTERNAL
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bool
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default y
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config SOC_I2S_SUPPORTS_PCM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM_TX
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bool
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default y
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config SOC_I2S_SUPPORTS_PCM2PDM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM_RX
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM2PCM
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bool
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default y
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config SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER
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bool
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default y
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config SOC_I2S_SUPPORTS_TX_SYNC_CNT
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bool
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default y
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config SOC_I2S_SUPPORTS_RX_RECOMB
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bool
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default y
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config SOC_I2S_SUPPORTS_TDM
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bool
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default y
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config SOC_I2S_PDM_MAX_TX_LINES
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int
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default 2
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config SOC_I2S_PDM_MAX_RX_LINES
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int
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default 4
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@@ -476,6 +476,25 @@ typedef enum {
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MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
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} soc_periph_mcpwm_carrier_clk_src_t;
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//////////////////////////////////////////////////I2S/////////////////////////////////////////////////////////////////
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/**
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* @brief I2S clock source
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL, SOC_MOD_CLK_RTC_FAST, I2S_CLK_SRC_EXTERNAL}
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/**
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* @brief I2S clock source enum
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Auto select maximum clock source as default source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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I2S_CLK_SRC_APLL = SOC_MOD_CLK_APLL, /*!< Select APLL as the source clock */
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I2S_CLK_SRC_RTC_FAST = SOC_MOD_CLK_RTC_FAST, /*!< Select RTC_FAST as the source clock */
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I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
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} soc_periph_i2s_clk_src_t;
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//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
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typedef enum {
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CLKOUT_SIG_MPLL_500M = 0, /*!< MPLL output at 500MHz */
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@@ -0,0 +1,131 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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#pragma once
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/**
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* @file regi2c_apll.h
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* @brief Register definitions for audio PLL (APLL)
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*
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* This file lists register fields of APLL, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* rtc_clk_apll_freq_set and rtc_clk_apll_enable function in rtc_clk.c.
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*/
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#define I2C_APLL 0X0C
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#define I2C_APLL_HOSTID 0
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#define I2C_APLL_IR_CAL_DELAY 0
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#define I2C_APLL_IR_CAL_DELAY_MSB 3
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#define I2C_APLL_IR_CAL_DELAY_LSB 0
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#define I2C_APLL_IR_CAL_RSTB 0
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#define I2C_APLL_IR_CAL_RSTB_MSB 4
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#define I2C_APLL_IR_CAL_RSTB_LSB 4
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#define I2C_APLL_IR_CAL_START 0
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#define I2C_APLL_IR_CAL_START_MSB 5
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#define I2C_APLL_IR_CAL_START_LSB 5
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#define I2C_APLL_IR_CAL_UNSTOP 0
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#define I2C_APLL_IR_CAL_UNSTOP_MSB 6
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#define I2C_APLL_IR_CAL_UNSTOP_LSB 6
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#define I2C_APLL_OC_ENB_FCAL 0
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#define I2C_APLL_OC_ENB_FCAL_MSB 7
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#define I2C_APLL_OC_ENB_FCAL_LSB 7
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#define I2C_APLL_IR_CAL_EXT_CAP 1
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#define I2C_APLL_IR_CAL_EXT_CAP_MSB 4
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#define I2C_APLL_IR_CAL_EXT_CAP_LSB 0
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#define I2C_APLL_IR_CAL_ENX_CAP 1
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#define I2C_APLL_IR_CAL_ENX_CAP_MSB 5
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#define I2C_APLL_IR_CAL_ENX_CAP_LSB 5
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#define I2C_APLL_OC_LBW 1
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#define I2C_APLL_OC_LBW_MSB 6
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#define I2C_APLL_OC_LBW_LSB 6
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#define I2C_APLL_IR_CAL_CK_DIV 2
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#define I2C_APLL_IR_CAL_CK_DIV_MSB 3
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#define I2C_APLL_IR_CAL_CK_DIV_LSB 0
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#define I2C_APLL_OC_DCHGP 2
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#define I2C_APLL_OC_DCHGP_MSB 6
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#define I2C_APLL_OC_DCHGP_LSB 4
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#define I2C_APLL_OC_ENB_VCON 2
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#define I2C_APLL_OC_ENB_VCON_MSB 7
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#define I2C_APLL_OC_ENB_VCON_LSB 7
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#define I2C_APLL_OR_CAL_CAP 3
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#define I2C_APLL_OR_CAL_CAP_MSB 4
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#define I2C_APLL_OR_CAL_CAP_LSB 0
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#define I2C_APLL_OR_CAL_UDF 3
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#define I2C_APLL_OR_CAL_UDF_MSB 5
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#define I2C_APLL_OR_CAL_UDF_LSB 5
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#define I2C_APLL_OR_CAL_OVF 3
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#define I2C_APLL_OR_CAL_OVF_MSB 6
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#define I2C_APLL_OR_CAL_OVF_LSB 6
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#define I2C_APLL_OR_CAL_END 3
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#define I2C_APLL_OR_CAL_END_MSB 7
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#define I2C_APLL_OR_CAL_END_LSB 7
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#define I2C_APLL_OR_OUTPUT_DIV 4
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#define I2C_APLL_OR_OUTPUT_DIV_MSB 4
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#define I2C_APLL_OR_OUTPUT_DIV_LSB 0
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#define I2C_APLL_OC_TSCHGP 4
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#define I2C_APLL_OC_TSCHGP_MSB 6
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#define I2C_APLL_OC_TSCHGP_LSB 6
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#define I2C_APLL_EN_FAST_CAL 4
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#define I2C_APLL_EN_FAST_CAL_MSB 7
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#define I2C_APLL_EN_FAST_CAL_LSB 7
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#define I2C_APLL_OC_DHREF_SEL 5
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#define I2C_APLL_OC_DHREF_SEL_MSB 1
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#define I2C_APLL_OC_DHREF_SEL_LSB 0
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#define I2C_APLL_OC_DLREF_SEL 5
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#define I2C_APLL_OC_DLREF_SEL_MSB 3
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#define I2C_APLL_OC_DLREF_SEL_LSB 2
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#define I2C_APLL_SDM_DITHER 5
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#define I2C_APLL_SDM_DITHER_MSB 4
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#define I2C_APLL_SDM_DITHER_LSB 4
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#define I2C_APLL_SDM_STOP 5
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#define I2C_APLL_SDM_STOP_MSB 5
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#define I2C_APLL_SDM_STOP_LSB 5
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#define I2C_APLL_SDM_RSTB 5
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#define I2C_APLL_SDM_RSTB_MSB 6
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#define I2C_APLL_SDM_RSTB_LSB 6
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#define I2C_APLL_OC_DVDD 6
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#define I2C_APLL_OC_DVDD_MSB 4
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#define I2C_APLL_OC_DVDD_LSB 0
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#define I2C_APLL_OC_REF_DIV 6
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#define I2C_APLL_OC_REF_DIV_MSB 7
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#define I2C_APLL_OC_REF_DIV_LSB 5
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#define I2C_APLL_DSDM2 7
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#define I2C_APLL_DSDM2_MSB 5
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#define I2C_APLL_DSDM2_LSB 0
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#define I2C_APLL_DSDM1 8
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#define I2C_APLL_DSDM1_MSB 7
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#define I2C_APLL_DSDM1_LSB 0
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#define I2C_APLL_DSDM0 9
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#define I2C_APLL_DSDM0_MSB 7
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#define I2C_APLL_DSDM0_LSB 0
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@@ -58,7 +58,7 @@
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#define SOC_RTC_FAST_MEM_SUPPORTED 1
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#define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14645
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#define SOC_RMT_SUPPORTED 1
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// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32S31] IDF-14771
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#define SOC_I2S_SUPPORTED 1
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#define SOC_SDM_SUPPORTED 1
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#define SOC_GPSPI_SUPPORTED 1
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#define SOC_LEDC_SUPPORTED 1
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@@ -390,13 +390,15 @@
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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// #define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */ // TODO: IDF-14771, IDF-14750
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#define SOC_CLK_APLL_SUPPORTED (1) /*!< Support Audio PLL */
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#define SOC_CLK_MPLL_SUPPORTED (1) /*!< Support MSPI PLL */ // TODO: IDF-14718
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#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
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#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
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#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */
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#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
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#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */
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/*-------------------------- Memory CAPS --------------------------*/
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#define SOC_ASYNCHRONOUS_BUS_ERROR_MODE (1)
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@@ -501,3 +503,23 @@
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#define SOC_BLE_SUBRATE_SUPPORTED (1) /*!< Support Bluetooth LE Connection Subrating */
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#define SOC_BLE_PERIODIC_ADV_WITH_RESPONSE (1) /*!< Support Bluetooth LE Periodic Advertising with Response (PAwR) */
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// #define SOC_BLE_ISO_SUPPORTED (1) /*!< Support Bluetooth ISO */
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/*-------------------------- I2S CAPS ----------------------------------------*/
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#define SOC_I2S_NUM (2U)
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#define SOC_I2S_HW_VERSION_2 (1)
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#define SOC_I2S_SUPPORTS_ETM (1)
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#define SOC_I2S_SUPPORTS_APLL (1)
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#define SOC_I2S_SUPPORTS_RTC_FAST (1) // Support RTC_FAST as I2S clock source
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#define SOC_I2S_SUPPORTS_EXTERNAL (1) // Support External clock source
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#define SOC_I2S_SUPPORTS_PCM (1)
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#define SOC_I2S_SUPPORTS_PDM (1)
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#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
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#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter
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#define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data
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#define SOC_I2S_SUPPORTS_PDM2PCM (1) // Support to input PDM format but read PCM format data with the help of PDM to PCM filter (only on I2S0)
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#define SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER (1)
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#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1) // Support TX synchronization count (ideal_cnt)
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#define SOC_I2S_SUPPORTS_RX_RECOMB (1) // Support RX recomb for DMA data format reorganization
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#define SOC_I2S_SUPPORTS_TDM (1)
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#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
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#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -10,10 +10,12 @@
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extern "C" {
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#endif
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/** I2S_INT_RAW_REG register
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#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1000)
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/** I2S_INT_RAW_REG(i) register
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* I2S interrupt raw register, valid in level.
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*/
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#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
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#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
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/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status bit for the i2s_rx_done_int interrupt
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*/
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@@ -50,10 +52,10 @@ extern "C" {
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#define I2S_TX_SYNC_INT_RAW_V 0x00000001U
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#define I2S_TX_SYNC_INT_RAW_S 4
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/** I2S_INT_ST_REG register
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/** I2S_INT_ST_REG(i) register
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* I2S interrupt status register.
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*/
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#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
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#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
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/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* The masked interrupt status bit for the i2s_rx_done_int interrupt
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*/
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@@ -90,10 +92,10 @@ extern "C" {
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#define I2S_TX_SYNC_INT_ST_V 0x00000001U
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#define I2S_TX_SYNC_INT_ST_S 4
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/** I2S_INT_ENA_REG register
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/** I2S_INT_ENA_REG(i) register
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* I2S interrupt enable register.
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*/
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#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
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#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
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/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* The interrupt enable bit for the i2s_rx_done_int interrupt
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*/
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@@ -130,10 +132,10 @@ extern "C" {
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#define I2S_TX_SYNC_INT_ENA_V 0x00000001U
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#define I2S_TX_SYNC_INT_ENA_S 4
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|
||||
/** I2S_INT_CLR_REG register
|
||||
/** I2S_INT_CLR_REG(i) register
|
||||
* I2S interrupt clear register.
|
||||
*/
|
||||
#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
|
||||
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
|
||||
/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the i2s_rx_done_int interrupt
|
||||
*/
|
||||
@@ -170,10 +172,10 @@ extern "C" {
|
||||
#define I2S_TX_SYNC_INT_CLR_V 0x00000001U
|
||||
#define I2S_TX_SYNC_INT_CLR_S 4
|
||||
|
||||
/** I2S_RX_CONF_REG register
|
||||
/** I2S_RX_CONF_REG(i) register
|
||||
* I2S RX configure register
|
||||
*/
|
||||
#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
|
||||
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
|
||||
/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset receiver
|
||||
*/
|
||||
@@ -322,10 +324,10 @@ extern "C" {
|
||||
#define I2S_RX_BCK_DIV_NUM_V 0x0000003FU
|
||||
#define I2S_RX_BCK_DIV_NUM_S 21
|
||||
|
||||
/** I2S_TX_CONF_REG register
|
||||
/** I2S_TX_CONF_REG(i) register
|
||||
* I2S TX configure register
|
||||
*/
|
||||
#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
|
||||
#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
|
||||
/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset transmitter
|
||||
*/
|
||||
@@ -498,10 +500,10 @@ extern "C" {
|
||||
#define I2S_SIG_LOOPBACK_V 0x00000001U
|
||||
#define I2S_SIG_LOOPBACK_S 30
|
||||
|
||||
/** I2S_RX_CONF1_REG register
|
||||
/** I2S_RX_CONF1_REG(i) register
|
||||
* I2S RX configure register 1
|
||||
*/
|
||||
#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
|
||||
#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
|
||||
/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
|
||||
* The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
|
||||
* T_bck
|
||||
@@ -535,10 +537,10 @@ extern "C" {
|
||||
#define I2S_RX_TDM_CHAN_BITS_V 0x0000001FU
|
||||
#define I2S_RX_TDM_CHAN_BITS_S 27
|
||||
|
||||
/** I2S_TX_CONF1_REG register
|
||||
/** I2S_TX_CONF1_REG(i) register
|
||||
* I2S TX configure register 1
|
||||
*/
|
||||
#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
|
||||
#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
|
||||
/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
|
||||
* The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
|
||||
* T_bck
|
||||
@@ -572,10 +574,10 @@ extern "C" {
|
||||
#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU
|
||||
#define I2S_TX_TDM_CHAN_BITS_S 27
|
||||
|
||||
/** I2S_RX_RECOMB_CTRL_REG register
|
||||
/** I2S_RX_RECOMB_CTRL_REG(i) register
|
||||
* I2S RX configure register 1
|
||||
*/
|
||||
#define I2S_RX_RECOMB_CTRL_REG (DR_REG_I2S_BASE + 0x30)
|
||||
#define I2S_RX_RECOMB_CTRL_REG(i) (REG_I2S_BASE(i) + 0x30)
|
||||
/** I2S_RX_RECOMB_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable i2s rx data recombination.
|
||||
*/
|
||||
@@ -599,10 +601,10 @@ extern "C" {
|
||||
#define I2S_RX_RECOMB_UPDATE_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_UPDATE_S 31
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH0_REG register
|
||||
/** I2S_RX_RECOMB_DMA_CH0_REG(i) register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_REG (DR_REG_I2S_BASE + 0x34)
|
||||
#define I2S_RX_RECOMB_DMA_CH0_REG(i) (REG_I2S_BASE(i) + 0x34)
|
||||
/** I2S_RX_RECOMB_DMA_CH0_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
@@ -634,10 +636,10 @@ extern "C" {
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH1_REG register
|
||||
/** I2S_RX_RECOMB_DMA_CH1_REG(i) register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_REG (DR_REG_I2S_BASE + 0x38)
|
||||
#define I2S_RX_RECOMB_DMA_CH1_REG(i) (REG_I2S_BASE(i) + 0x38)
|
||||
/** I2S_RX_RECOMB_DMA_CH1_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
@@ -669,10 +671,10 @@ extern "C" {
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH2_REG register
|
||||
/** I2S_RX_RECOMB_DMA_CH2_REG(i) register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_REG (DR_REG_I2S_BASE + 0x3c)
|
||||
#define I2S_RX_RECOMB_DMA_CH2_REG(i) (REG_I2S_BASE(i) + 0x3c)
|
||||
/** I2S_RX_RECOMB_DMA_CH2_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
@@ -704,10 +706,10 @@ extern "C" {
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH3_REG register
|
||||
/** I2S_RX_RECOMB_DMA_CH3_REG(i) register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_REG (DR_REG_I2S_BASE + 0x40)
|
||||
#define I2S_RX_RECOMB_DMA_CH3_REG(i) (REG_I2S_BASE(i) + 0x40)
|
||||
/** I2S_RX_RECOMB_DMA_CH3_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
@@ -739,10 +741,10 @@ extern "C" {
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S 13
|
||||
|
||||
/** I2S_TX_PCM2PDM_CONF_REG register
|
||||
/** I2S_TX_PCM2PDM_CONF_REG(i) register
|
||||
* I2S TX PCM2PDM configuration register
|
||||
*/
|
||||
#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44)
|
||||
#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x44)
|
||||
/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
|
||||
* I2S TX PDM OSR2 value
|
||||
*/
|
||||
@@ -821,10 +823,10 @@ extern "C" {
|
||||
#define I2S_PCM2PDM_CONV_EN_V 0x00000001U
|
||||
#define I2S_PCM2PDM_CONV_EN_S 25
|
||||
|
||||
/** I2S_TX_PCM2PDM_CONF1_REG register
|
||||
/** I2S_TX_PCM2PDM_CONF1_REG(i) register
|
||||
* I2S TX PCM2PDM configuration register
|
||||
*/
|
||||
#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48)
|
||||
#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x48)
|
||||
/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
|
||||
* I2S TX PDM Fp
|
||||
*/
|
||||
@@ -856,10 +858,10 @@ extern "C" {
|
||||
#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U
|
||||
#define I2S_TX_IIR_HP_MULT12_0_S 23
|
||||
|
||||
/** I2S_RX_PDM2PCM_CONF_REG register
|
||||
/** I2S_RX_PDM2PCM_CONF_REG(i) register
|
||||
* I2S RX configure register
|
||||
*/
|
||||
#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x4c)
|
||||
#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x4c)
|
||||
/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
|
||||
* 1: Enable PDM2PCM RX mode. 0: DIsable.
|
||||
*/
|
||||
@@ -906,10 +908,10 @@ extern "C" {
|
||||
#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U
|
||||
#define I2S_RX_IIR_HP_MULT12_0_S 29
|
||||
|
||||
/** I2S_RX_TDM_CTRL_REG register
|
||||
/** I2S_RX_TDM_CTRL_REG(i) register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
|
||||
#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
|
||||
/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
|
||||
* 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
|
||||
* input 0 in this channel.
|
||||
@@ -1053,10 +1055,10 @@ extern "C" {
|
||||
#define I2S_RX_TDM_BITS_MODE_DET_EN_V 0x00000001U
|
||||
#define I2S_RX_TDM_BITS_MODE_DET_EN_S 20
|
||||
|
||||
/** I2S_TX_TDM_CTRL_REG register
|
||||
/** I2S_TX_TDM_CTRL_REG(i) register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
|
||||
#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
|
||||
/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
|
||||
* 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
|
||||
* 0 in this channel.
|
||||
@@ -1209,10 +1211,10 @@ extern "C" {
|
||||
#define I2S_TX_TDM_BITS_MODE_DET_EN_V 0x00000001U
|
||||
#define I2S_TX_TDM_BITS_MODE_DET_EN_S 21
|
||||
|
||||
/** I2S_RX_TIMING_REG register
|
||||
/** I2S_RX_TIMING_REG(i) register
|
||||
* I2S RX timing control register
|
||||
*/
|
||||
#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
|
||||
#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
|
||||
/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
|
||||
* The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
|
||||
* delay by neg edge. 3: not used.
|
||||
@@ -1278,10 +1280,10 @@ extern "C" {
|
||||
#define I2S_RX_BCK_IN_DM_V 0x00000003U
|
||||
#define I2S_RX_BCK_IN_DM_S 28
|
||||
|
||||
/** I2S_TX_TIMING_REG register
|
||||
/** I2S_TX_TIMING_REG(i) register
|
||||
* I2S TX timing control register
|
||||
*/
|
||||
#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
|
||||
#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
|
||||
/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
|
||||
* The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
|
||||
* delay by neg edge. 3: not used.
|
||||
@@ -1331,10 +1333,10 @@ extern "C" {
|
||||
#define I2S_TX_BCK_IN_DM_V 0x00000003U
|
||||
#define I2S_TX_BCK_IN_DM_S 28
|
||||
|
||||
/** I2S_LC_HUNG_CONF_REG register
|
||||
/** I2S_LC_HUNG_CONF_REG(i) register
|
||||
* I2S HUNG configure register.
|
||||
*/
|
||||
#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
|
||||
#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
|
||||
/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
|
||||
* the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
|
||||
* when fifo hung counter is equal to this value
|
||||
@@ -1359,10 +1361,10 @@ extern "C" {
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001U
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA_S 11
|
||||
|
||||
/** I2S_RXEOF_NUM_REG register
|
||||
/** I2S_RXEOF_NUM_REG(i) register
|
||||
* I2S RX data number control register.
|
||||
*/
|
||||
#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
|
||||
#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
|
||||
/** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64;
|
||||
* The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0])
|
||||
* . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
|
||||
@@ -1372,10 +1374,10 @@ extern "C" {
|
||||
#define I2S_RX_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_EOF_NUM_S 0
|
||||
|
||||
/** I2S_CONF_SIGLE_DATA_REG register
|
||||
/** I2S_CONF_SIGLE_DATA_REG(i) register
|
||||
* I2S signal data register
|
||||
*/
|
||||
#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
|
||||
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
|
||||
/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
* The configured constant channel data to be sent out.
|
||||
*/
|
||||
@@ -1384,10 +1386,10 @@ extern "C" {
|
||||
#define I2S_SINGLE_DATA_V 0xFFFFFFFFU
|
||||
#define I2S_SINGLE_DATA_S 0
|
||||
|
||||
/** I2S_STATE_REG register
|
||||
/** I2S_STATE_REG(i) register
|
||||
* I2S TX status register
|
||||
*/
|
||||
#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
|
||||
#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
|
||||
/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
|
||||
* 1: i2s_tx is idle state. 0: i2s_tx is working.
|
||||
*/
|
||||
@@ -1396,10 +1398,10 @@ extern "C" {
|
||||
#define I2S_TX_IDLE_V 0x00000001U
|
||||
#define I2S_TX_IDLE_S 0
|
||||
|
||||
/** I2S_ETM_CONF_REG register
|
||||
/** I2S_ETM_CONF_REG(i) register
|
||||
* I2S ETM configure register
|
||||
*/
|
||||
#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
|
||||
#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
|
||||
/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64;
|
||||
* I2S ETM send x words event. When sending word number of
|
||||
* reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event.
|
||||
@@ -1417,10 +1419,10 @@ extern "C" {
|
||||
#define I2S_ETM_RX_RECEIVE_WORD_NUM_V 0x00003FFFU
|
||||
#define I2S_ETM_RX_RECEIVE_WORD_NUM_S 14
|
||||
|
||||
/** I2S_IDEAL_CNT_REG register
|
||||
/** I2S_IDEAL_CNT_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74)
|
||||
#define I2S_IDEAL_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
|
||||
/** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0;
|
||||
* tx fifo counter ideal value.
|
||||
*/
|
||||
@@ -1429,10 +1431,10 @@ extern "C" {
|
||||
#define I2S_TX_IDEAL_CNT_V 0x7FFFFFFFU
|
||||
#define I2S_TX_IDEAL_CNT_S 0
|
||||
|
||||
/** I2S_FIFO_CNT_REG register
|
||||
/** I2S_FIFO_CNT_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78)
|
||||
#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
|
||||
/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
|
||||
* tx fifo counter value.
|
||||
*/
|
||||
@@ -1448,10 +1450,10 @@ extern "C" {
|
||||
#define I2S_TX_FIFO_CNT_RST_V 0x00000001U
|
||||
#define I2S_TX_FIFO_CNT_RST_S 31
|
||||
|
||||
/** I2S_BCK_CNT_REG register
|
||||
/** I2S_BCK_CNT_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c)
|
||||
#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x7c)
|
||||
/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
|
||||
* tx bck counter value.
|
||||
*/
|
||||
@@ -1467,10 +1469,10 @@ extern "C" {
|
||||
#define I2S_TX_BCK_CNT_RST_V 0x00000001U
|
||||
#define I2S_TX_BCK_CNT_RST_S 31
|
||||
|
||||
/** I2S_CNT_DIFF_REG register
|
||||
/** I2S_CNT_DIFF_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80)
|
||||
#define I2S_CNT_DIFF_REG(i) (REG_I2S_BASE(i) + 0x80)
|
||||
/** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0;
|
||||
* tx bck counter value.
|
||||
*/
|
||||
@@ -1486,10 +1488,10 @@ extern "C" {
|
||||
#define I2S_TX_CNT_DIFF_RST_V 0x00000001U
|
||||
#define I2S_TX_CNT_DIFF_RST_S 31
|
||||
|
||||
/** I2S_SYNC_SW_THRES_REG register
|
||||
/** I2S_SYNC_SW_THRES_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84)
|
||||
#define I2S_SYNC_SW_THRES_REG(i) (REG_I2S_BASE(i) + 0x84)
|
||||
/** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0;
|
||||
* tx fifo counter difference software threshold value, when difference larger than
|
||||
* this threshold, interrupt will occur and hardware sync will not be executed.
|
||||
@@ -1499,10 +1501,10 @@ extern "C" {
|
||||
#define I2S_TX_CNT_DIFF_SW_THRES_V 0x7FFFFFFFU
|
||||
#define I2S_TX_CNT_DIFF_SW_THRES_S 0
|
||||
|
||||
/** I2S_SYNC_HW_THRES_REG register
|
||||
/** I2S_SYNC_HW_THRES_REG(i) register
|
||||
* I2S sync counter register
|
||||
*/
|
||||
#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88)
|
||||
#define I2S_SYNC_HW_THRES_REG(i) (REG_I2S_BASE(i) + 0x88)
|
||||
/** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0;
|
||||
* tx fifo counter difference hardware threshold value, which means that only when
|
||||
* difference larger than this threshold will hardware start hardware sync.
|
||||
@@ -1512,10 +1514,10 @@ extern "C" {
|
||||
#define I2S_TX_CNT_DIFF_HW_THRES_V 0x7FFFFFFFU
|
||||
#define I2S_TX_CNT_DIFF_HW_THRES_S 0
|
||||
|
||||
/** I2S_HW_SYNC_CONF_REG register
|
||||
/** I2S_HW_SYNC_CONF_REG(i) register
|
||||
* I2S TX hardware sync function configuration register
|
||||
*/
|
||||
#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c)
|
||||
#define I2S_HW_SYNC_CONF_REG(i) (REG_I2S_BASE(i) + 0x8c)
|
||||
/** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable
|
||||
*/
|
||||
@@ -1532,10 +1534,10 @@ extern "C" {
|
||||
#define I2S_TX_HW_SYNC_SUPPL_MODE_V 0x00000001U
|
||||
#define I2S_TX_HW_SYNC_SUPPL_MODE_S 1
|
||||
|
||||
/** I2S_HW_SYNC_DATA_REG register
|
||||
/** I2S_HW_SYNC_DATA_REG(i) register
|
||||
* I2S TX hardware sync function configuration register
|
||||
*/
|
||||
#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90)
|
||||
#define I2S_HW_SYNC_DATA_REG(i) (REG_I2S_BASE(i) + 0x90)
|
||||
/** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configure the i2s tx hardware sync supplementation data when
|
||||
* I2S_TX_HW_SYNC_SUPPL_MODE is 1.
|
||||
@@ -1545,10 +1547,10 @@ extern "C" {
|
||||
#define I2S_TX_HW_SYNC_SUPPL_DATA_V 0xFFFFFFFFU
|
||||
#define I2S_TX_HW_SYNC_SUPPL_DATA_S 0
|
||||
|
||||
/** I2S_DESTINATION_REG register
|
||||
/** I2S_DESTINATION_REG(i) register
|
||||
* I2S TX status register
|
||||
*/
|
||||
#define I2S_DESTINATION_REG (DR_REG_I2S_BASE + 0xf4)
|
||||
#define I2S_DESTINATION_REG(i) (REG_I2S_BASE(i) + 0xf4)
|
||||
/** I2S_RX_DESTINATION : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to configure the data destination of i2s rx. 1: ble. 0: gdma.
|
||||
*/
|
||||
@@ -1564,10 +1566,10 @@ extern "C" {
|
||||
#define I2S_TX_DESTINATION_V 0x00000001U
|
||||
#define I2S_TX_DESTINATION_S 1
|
||||
|
||||
/** I2S_CLK_GATE_REG register
|
||||
/** I2S_CLK_GATE_REG(i) register
|
||||
* Clock gate register
|
||||
*/
|
||||
#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8)
|
||||
#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0xf8)
|
||||
/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* set this bit to enable clock gate
|
||||
*/
|
||||
@@ -1576,10 +1578,10 @@ extern "C" {
|
||||
#define I2S_CLK_EN_V 0x00000001U
|
||||
#define I2S_CLK_EN_S 0
|
||||
|
||||
/** I2S_DATE_REG register
|
||||
/** I2S_DATE_REG(i) register
|
||||
* Version control register
|
||||
*/
|
||||
#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc)
|
||||
#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0xfc)
|
||||
/** I2S_DATE : R/W; bitpos: [27:0]; default: 38813744;
|
||||
* I2S version control register
|
||||
*/
|
||||
|
||||
@@ -1282,6 +1282,8 @@ typedef struct {
|
||||
volatile i2s_date_reg_t date;
|
||||
} i2s_dev_t;
|
||||
|
||||
extern i2s_dev_t I2S0;
|
||||
extern i2s_dev_t I2S1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(i2s_dev_t) == 0x100, "Invalid size of i2s_dev_t structure");
|
||||
|
||||
Reference in New Issue
Block a user