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feat(i2s): support i2s & apll on esp32s31
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@@ -16,6 +16,8 @@
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#include "soc/lp_clkrst_struct.h"
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#include "soc/hp_alive_sys_reg.h"
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#include "soc/hp_alive_sys_struct.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_apll.h"
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#include "soc/pmu_reg.h"
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#include "hal/clkout_channel.h"
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#include "hal/assert.h"
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@@ -463,7 +465,12 @@ static inline __attribute__((always_inline)) bool clk_ll_mpll_calibration_is_don
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
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{
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// TODO: IDF-14771, IDF-14750
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uint32_t apll_sdm = HAL_FORCE_READ_U32_REG_FIELD(LP_CLKRST.apll_sdm, apll_sdm);
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*o_div = HAL_FORCE_READ_U32_REG_FIELD(LP_CLKRST.apll_div, apll_out_div);
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*sdm0 = apll_sdm & 0xFF;
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*sdm1 = (apll_sdm >> 8) & 0xFF;
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*sdm2 = (apll_sdm >> 16) & 0x3F;
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}
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/**
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@@ -476,7 +483,8 @@ static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
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{
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// TODO: IDF-14771, IDF-14750
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_CLKRST.apll_div, apll_out_div, o_div);
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HAL_FORCE_MODIFY_U32_REG_FIELD(LP_CLKRST.apll_sdm, apll_sdm, (sdm2 << 16) | (sdm1 << 8) | sdm0);
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}
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/**
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@@ -484,7 +492,9 @@ static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_
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*/
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static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
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{
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// TODO: IDF-14771, IDF-14750
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REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1);
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REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2);
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REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_3);
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}
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/**
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@@ -494,8 +504,7 @@ static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(vo
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*/
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static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
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{
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// TODO: IDF-14771, IDF-14750
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return 0;
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return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_PLLA_CAL_END);
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}
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/**
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