From 2c4ad9caad589d1b46816eb0b9a9b057d8dadae8 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 13 Aug 2026 19:49:24 +0800 Subject: [PATCH] fix(esp_hw_support): fix esp32p4 PVT clock lost --- components/esp_hw_support/port/esp32p4/esp_clk_tree.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c index 9e202c67802..0fc482d081b 100644 --- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c @@ -189,7 +189,10 @@ void esp_clk_tree_initialize(void) _clk_gate_ll_ref_50m_clk_en(false); _clk_gate_ll_ref_80m_clk_en(false); _clk_gate_ll_ref_120m_clk_en(false); +#if !CONFIG_ESP_ENABLE_PVT + // PLL_F160M must always on if PVT is enabled. _clk_gate_ll_ref_160m_clk_en(false); +#endif _clk_gate_ll_ref_240m_clk_en(false); s_clk_tree_initialized = true; } @@ -315,7 +318,10 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) case SOC_MOD_CLK_PLL_F25M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F25M; break; case SOC_MOD_CLK_PLL_F80M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F80M; break; case SOC_MOD_CLK_PLL_F120M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F120M; break; +#if !CONFIG_ESP_ENABLE_PVT + // PLL_F160M must always on if PVT is enabled. case SOC_MOD_CLK_PLL_F160M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F160M; break; +#endif case SOC_MOD_CLK_PLL_F240M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F240M; break; default: // Derived PLL clocks (PLL_F50M, ...) that participate in the shared