feat(uart): add glitch filter functionality for UART

Closes https://github.com/espressif/esp-idf/issues/17847
This commit is contained in:
Song Ruo Jing
2025-12-24 22:28:15 +08:00
parent 77aa76ecc4
commit 8baea2e4a0
24 changed files with 703 additions and 60 deletions

View File

@@ -34,12 +34,13 @@ extern "C" {
*/
typedef struct {
int baud_rate; /*!< UART baud rate
Note that the actual baud rate set could have a slight deviation from the user-configured value due to rounding error*/
uart_word_length_t data_bits; /*!< UART byte size*/
uart_parity_t parity; /*!< UART parity mode*/
uart_stop_bits_t stop_bits; /*!< UART stop bits*/
uart_hw_flowcontrol_t flow_ctrl; /*!< UART HW flow control mode (cts/rts)*/
uint8_t rx_flow_ctrl_thresh; /*!< UART HW RTS threshold*/
Note that the actual baud rate set could have a slight deviation from the user-configured value due to rounding error */
uart_word_length_t data_bits; /*!< UART byte size */
uart_parity_t parity; /*!< UART parity mode */
uart_stop_bits_t stop_bits; /*!< UART stop bits */
uart_hw_flowcontrol_t flow_ctrl; /*!< UART HW flow control mode (cts/rts) */
uint8_t rx_flow_ctrl_thresh; /*!< UART HW RTS threshold */
uint32_t rx_glitch_filt_thresh; /*!< The width of the glitch on the RX signal to be filtered (unit: ns). If set to 0, then RX signal filter is disabled. */
union {
uart_sclk_t source_clk; /*!< UART source clock selection */
#if (SOC_UART_LP_NUM >= 1)
@@ -896,6 +897,7 @@ typedef struct {
int rx_io_num; /*!< GPIO pin number for the incoming signal */
uart_sclk_t source_clk; /*!< The higher the frequency of the clock source, the more accurate the detected bitrate value;
The slower the frequency of the clock source, the slower the bitrate can be measured */
uint32_t rx_glitch_filt_thresh; /*!< The width of the glitch on the incoming signal to be filtered (unit: ns). If set to 0, then glitch filter is disabled. */
} uart_bitrate_detect_config_t;
/**