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feat(uart): add glitch filter functionality for UART
Closes https://github.com/espressif/esp-idf/issues/17847
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@@ -186,10 +186,9 @@ TEST_CASE("I3C master clock frequency test", "[i3c]")
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i3c_master_i2c_device_handle_t dev_1;
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TEST_ESP_OK(i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_1, &dev_1));
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uart_bitrate_detect_config_t conf = {
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.rx_io_num = I3C_MASTER_SCL_IO,
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.source_clk = UART_SCLK_DEFAULT,
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};
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uart_bitrate_detect_config_t conf = {};
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conf.rx_io_num = I3C_MASTER_SCL_IO;
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conf.source_clk = UART_SCLK_DEFAULT;
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uart_bitrate_res_t res = {};
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uart_detect_bitrate_start(UART_NUM_1, &conf);
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