mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
refactor(clk): split clock HAL into separate component
This commit is contained in:
Song Ruo Jing
morris
@@ -1,78 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/gpio_ll.h"
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#include "hal/assert.h"
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uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
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{
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switch (cpu_clk_src) {
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case SOC_CPU_CLK_SRC_XTAL:
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return clk_hal_xtal_get_freq_mhz();
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case SOC_CPU_CLK_SRC_PLL_F160M:
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return CLK_LL_PLL_160M_FREQ_MHZ;
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case SOC_CPU_CLK_SRC_RC_FAST:
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return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
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default:
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// Unknown CPU_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_cpu_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_cpu_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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static uint32_t clk_hal_ahb_get_freq_hz(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t divider = clk_ll_ahb_get_divider();
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return clk_hal_soc_root_get_freq_mhz(source) * MHZ / divider;
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}
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uint32_t clk_hal_apb_get_freq_hz(void)
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{
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return clk_hal_ahb_get_freq_hz() / clk_ll_apb_get_divider();
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}
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uint32_t clk_hal_lp_slow_get_freq_hz(void)
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{
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switch (clk_ll_rtc_slow_get_src()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
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return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
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return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
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return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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default:
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// Unknown RTC_SLOW_CLK mux input
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HAL_ASSERT(false);
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return 0;
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}
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}
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uint32_t clk_hal_xtal_get_freq_mhz(void)
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{
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uint32_t freq = clk_ll_xtal_get_freq_mhz();
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HAL_ASSERT(freq == SOC_XTAL_FREQ_40M);
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return freq;
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}
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void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)
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{
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gpio_ll_set_pin_ctrl(clk_sig, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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void clk_hal_clock_output_teardown(clock_out_channel_t channel_id)
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{
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gpio_ll_set_pin_ctrl(0, CLKOUT_CHANNEL_MASK(channel_id), CLKOUT_CHANNEL_SHIFT(channel_id));
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}
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@@ -1,637 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/pcr_struct.h"
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#include "soc/lp_clkrst_struct.h"
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#include "soc/pmu_reg.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_bbpll.h"
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#include "hal/assert.h"
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#include "hal/log.h"
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#include "esp32c61/rom/rtc.h"
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#include "hal/misc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MHZ (1000000)
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#define CLK_LL_PLL_80M_FREQ_MHZ (80)
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#define CLK_LL_PLL_120M_FREQ_MHZ (120)
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#define CLK_LL_PLL_160M_FREQ_MHZ (160)
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#define CLK_LL_PLL_480M_FREQ_MHZ (480)
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#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
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.dac = 7, \
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.dres = 0, \
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.dgm = 7, \
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.dbuf = 1, \
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}
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// Fix default division factor for the RC_FAST clock for calibration to be 32
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#define CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS 5
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/**
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* @brief XTAL32K_CLK enable modes
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*/
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typedef enum {
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CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL, //!< Enable the external 32kHz crystal for XTAL32K_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL, //!< Enable the external clock signal for OSC_SLOW_CLK
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CLK_LL_XTAL32K_ENABLE_MODE_BOOTSTRAP, //!< Bootstrap the crystal oscillator for faster XTAL32K_CLK start up */
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} clk_ll_xtal32k_enable_mode_t;
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/**
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* @brief XTAL32K_CLK configuration structure
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*/
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typedef struct {
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uint32_t dac : 6;
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uint32_t dres : 3;
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uint32_t dgm : 3;
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uint32_t dbuf: 1;
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} clk_ll_xtal32k_config_t;
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/**
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* @brief Power up BBPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
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{
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SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C |
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PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
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SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
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}
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/**
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* @brief Power down BBPLL circuit
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
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{
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SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG) ;
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SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_BBPLL | PMU_TIE_LOW_XPD_BBPLL_I2C);
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}
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/**
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* @brief Release the root clock source locked by PMU
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_clk_src_lock_release(void)
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{
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SET_PERI_REG_MASK(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_SYS_CLK_SEL);
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}
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/**
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* @brief Enable the 32kHz crystal oscillator
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*
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* @param mode Used to determine the xtal32k configuration parameters
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_enable(clk_ll_xtal32k_enable_mode_t mode)
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{
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if (mode == CLK_LL_XTAL32K_ENABLE_MODE_EXTERNAL) {
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// No need to configure anything for OSC_SLOW_CLK
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return;
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}
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// Configure xtal32k
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clk_ll_xtal32k_config_t cfg = CLK_LL_XTAL32K_CONFIG_DEFAULT();
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LP_CLKRST.xtal32k.dac_xtal32k = cfg.dac;
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LP_CLKRST.xtal32k.dres_xtal32k = cfg.dres;
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LP_CLKRST.xtal32k.dgm_xtal32k = cfg.dgm;
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LP_CLKRST.xtal32k.dbuf_xtal32k = cfg.dbuf;
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// Enable xtal32k xpd
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SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
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}
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/**
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* @brief Disable the 32kHz crystal oscillator
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_disable(void)
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{
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// Disable xtal32k xpd
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CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K);
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}
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/**
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* @brief Get the state of the 32kHz crystal clock
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*
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* @return True if the 32kHz XTAL is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void)
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{
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return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_XTAL32K) == 1;
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}
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/**
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* @brief Enable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
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{
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SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
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}
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/**
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* @brief Disable the internal oscillator output for RC_FAST_CLK
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
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{
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CLEAR_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK);
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}
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/**
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* @brief Get the state of the internal oscillator for RC_FAST_CLK
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*
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* @return True if the oscillator is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_is_enabled(void)
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{
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return REG_GET_FIELD(PMU_HP_SLEEP_LP_CK_POWER_REG, PMU_HP_SLEEP_XPD_FOSC_CLK) == 1;
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}
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/**
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* @brief Enable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_enable(void)
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{
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LP_CLKRST.clk_to_hp.icg_hp_fosc = 1;
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}
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/**
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* @brief Disable the digital RC_FAST_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_rc_fast_digi_disable(void)
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{
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LP_CLKRST.clk_to_hp.icg_hp_fosc = 0;
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}
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/**
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* @brief Get the state of the digital RC_FAST_CLK
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*
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* @return True if the digital RC_FAST_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_rc_fast_digi_is_enabled(void)
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{
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return LP_CLKRST.clk_to_hp.icg_hp_fosc;
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}
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/**
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* @brief Enable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_enable(void)
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{
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LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 1;
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}
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/**
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* @brief Disable the digital XTAL32K_CLK, which is used to support peripherals.
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*/
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static inline __attribute__((always_inline)) void clk_ll_xtal32k_digi_disable(void)
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{
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LP_CLKRST.clk_to_hp.icg_hp_xtal32k = 0;
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}
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/**
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* @brief Get the state of the digital XTAL32K_CLK
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*
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* @return True if the digital XTAL32K_CLK is enabled
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*/
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static inline __attribute__((always_inline)) bool clk_ll_xtal32k_digi_is_enabled(void)
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{
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return LP_CLKRST.clk_to_hp.icg_hp_xtal32k;
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}
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/**
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* @brief Get XTAL_CLK frequency
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*
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* @return Main XTAL clock frequency, in MHz.
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void)
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{
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return PCR.sysclk_conf.clk_xtal_freq;
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}
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#define clk_ll_xtal_load_freq_mhz() clk_ll_xtal_get_freq_mhz()
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/**
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* @brief Get SPLL_CLK frequency
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*
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* @return PLL clock frequency, in MHz. Returns 0 if register field value is invalid.
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*/
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static inline __attribute__((always_inline)) uint32_t clk_ll_bbpll_get_freq_mhz(void)
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{
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// The target has a fixed 480MHz SPLL
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return CLK_LL_PLL_480M_FREQ_MHZ;
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}
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/**
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* @brief Set SPLL frequency from XTAL source (Digital part)
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*
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* @param pll_freq_mhz PLL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint32_t pll_freq_mhz)
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{
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// The target SPLL is fixed to 480MHz
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// Do nothing
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HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
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}
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/** TODO
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* @brief Set SPLL frequency from XTAL source (Analog part)
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*
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* @param pll_freq_mhz PLL frequency, in MHz
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* @param xtal_freq_mhz XTAL frequency, in MHz
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*/
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static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
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{
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HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ);
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uint8_t div_ref;
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uint8_t div7_0;
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uint8_t dchgp = 5;
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uint8_t dbias = 3;
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uint8_t href = 3;
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uint8_t lref = 1;
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/* Configure 480M PLL */
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switch (xtal_freq_mhz) {
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case SOC_XTAL_FREQ_40M:
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default:
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div_ref = 0;
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div7_0 = 8;
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break;
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}
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uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
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uint8_t i2c_bbpll_div_7_0 = div7_0;
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, lref);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, href);
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REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
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}
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/**
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* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
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*/
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static inline __attribute__((always_inline)) void clk_ll_bus_update(void)
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{
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PCR.bus_clk_update.bus_clock_update = 1;
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while (PCR.bus_clk_update.bus_clock_update);
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}
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/**
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* @brief Select the clock source for CPU_CLK (SOC Clock Root)
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*
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* @param in_sel One of the clock sources in soc_cpu_clk_src_t
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*/
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static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk_src_t in_sel)
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{
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switch (in_sel) {
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case SOC_CPU_CLK_SRC_XTAL:
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PCR.sysclk_conf.soc_clk_sel = 0;
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break;
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case SOC_CPU_CLK_SRC_RC_FAST:
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PCR.sysclk_conf.soc_clk_sel = 1;
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break;
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case SOC_CPU_CLK_SRC_PLL_F160M:
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PCR.sysclk_conf.soc_clk_sel = 2;
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break;
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default:
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// Unsupported SOC_CLK mux input sel
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abort();
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}
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}
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/**
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* @brief Get the clock source for CPU_CLK (SOC Clock Root)
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*
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* @return Currently selected clock source (one of soc_cpu_clk_src_t values)
|
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*/
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static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_src(void)
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{
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uint32_t clk_sel = PCR.sysclk_conf.soc_clk_sel;
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switch (clk_sel) {
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case 0:
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return SOC_CPU_CLK_SRC_XTAL;
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case 1:
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return SOC_CPU_CLK_SRC_RC_FAST;
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case 2:
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return SOC_CPU_CLK_SRC_PLL_F160M;
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default:
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// Invalid SOC_CLK_SEL value
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return SOC_CPU_CLK_SRC_INVALID;
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}
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||||
}
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||||
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/**
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* @brief Set CPU_CLK's divider
|
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*
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* SOC_ROOT_CLK ------> CPU_CLK
|
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*
|
||||
* @param divider Divider. (PCR_CPU_DIV_NUM + 1) = divider.
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||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_cpu_set_divider(uint32_t divider)
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||||
{
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||||
HAL_ASSERT(divider >= 1);
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num, (divider) - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get CPU_CLK's divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_CPU_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_cpu_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.cpu_freq_conf, cpu_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set AHB_CLK's divider
|
||||
*
|
||||
* SOC_ROOT_CLK ------> AHB_CLK
|
||||
* Constraint: f_ahb <= 40 MHz, f_cpu = n * f_ahb
|
||||
*
|
||||
* @param divider Divider. (PCR_AHB_DIV_NUM + 1) = divider.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_ahb_set_divider(uint32_t divider)
|
||||
{
|
||||
HAL_ASSERT(divider >= 1);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get AHB_CLK's divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_AHB_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_ahb_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.ahb_freq_conf, ahb_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set APB_CLK divider. freq of APB_CLK = freq of AHB_CLK / divider
|
||||
*
|
||||
* @param divider Divider. PCR_APB_DIV_NUM = divider - 1.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_apb_set_divider(uint32_t divider)
|
||||
{
|
||||
// AHB ------> APB
|
||||
// Divider option: 1, 2, 4 (PCR_APB_DIV_NUM=0, 1, 3)
|
||||
HAL_ASSERT(divider == 1 || divider == 2 || divider == 4);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num, divider - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get APB_CLK divider
|
||||
*
|
||||
* @return Divider. Divider = (PCR_APB_DIV_NUM + 1).
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(void)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the frequency calculation clock source for timergroup0
|
||||
*
|
||||
* @param clk_sel One of the clock sources in soc_clk_freq_calculation_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_freq_calulation_set_target(soc_clk_freq_calculation_src_t clk_sel)
|
||||
{
|
||||
int timg_cali_clk_sel = -1;
|
||||
|
||||
switch (clk_sel) {
|
||||
case CLK_CAL_32K_XTAL:
|
||||
timg_cali_clk_sel = 1;
|
||||
break;
|
||||
case CLK_CAL_32K_OSC_SLOW:
|
||||
timg_cali_clk_sel = 2;
|
||||
break;
|
||||
case CLK_CAL_RC_SLOW:
|
||||
timg_cali_clk_sel = 3;
|
||||
break;
|
||||
case CLK_CAL_RC_FAST:
|
||||
timg_cali_clk_sel = 4;
|
||||
break;
|
||||
default:
|
||||
// Unsupported CLK_CAL mux input
|
||||
abort();
|
||||
}
|
||||
|
||||
if (timg_cali_clk_sel >= 0) {
|
||||
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the frequency division factor of RC_FAST clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_slow_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_set_src(soc_rtc_slow_clk_src_t in_sel)
|
||||
{
|
||||
switch (in_sel) {
|
||||
case SOC_RTC_SLOW_CLK_SRC_RC_SLOW:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 0;
|
||||
break;
|
||||
case SOC_RTC_SLOW_CLK_SRC_XTAL32K:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 1;
|
||||
break;
|
||||
case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW:
|
||||
LP_CLKRST.lp_clk_conf.slow_clk_sel = 3;
|
||||
break;
|
||||
default:
|
||||
// Unsupported RTC_SLOW_CLK mux input sel
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_SLOW_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_slow_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_slow_clk_src_t clk_ll_rtc_slow_get_src(void)
|
||||
{
|
||||
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.slow_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_RTC_SLOW_CLK_SRC_RC_SLOW;
|
||||
case 1:
|
||||
return SOC_RTC_SLOW_CLK_SRC_XTAL32K;
|
||||
case 3:
|
||||
return SOC_RTC_SLOW_CLK_SRC_OSC_SLOW;
|
||||
default:
|
||||
return SOC_RTC_SLOW_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @param in_sel One of the clock sources in soc_rtc_fast_clk_src_t
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_fast_set_src(soc_rtc_fast_clk_src_t in_sel)
|
||||
{
|
||||
switch (in_sel) {
|
||||
case SOC_RTC_FAST_CLK_SRC_RC_FAST:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 0;
|
||||
break;
|
||||
case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 1;
|
||||
break;
|
||||
case SOC_RTC_FAST_CLK_SRC_XTAL:
|
||||
LP_CLKRST.lp_clk_conf.fast_clk_sel = 2;
|
||||
break;
|
||||
default:
|
||||
// Unsupported RTC_FAST_CLK mux input sel
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the clock source for RTC_FAST_CLK
|
||||
*
|
||||
* @return Currently selected clock source (one of soc_rtc_fast_clk_src_t values)
|
||||
*/
|
||||
static inline __attribute__((always_inline)) soc_rtc_fast_clk_src_t clk_ll_rtc_fast_get_src(void)
|
||||
{
|
||||
uint32_t clk_sel = LP_CLKRST.lp_clk_conf.fast_clk_sel;
|
||||
switch (clk_sel) {
|
||||
case 0:
|
||||
return SOC_RTC_FAST_CLK_SRC_RC_FAST;
|
||||
case 1:
|
||||
return SOC_RTC_FAST_CLK_SRC_XTAL_D2;
|
||||
case 2:
|
||||
return SOC_RTC_FAST_CLK_SRC_XTAL;
|
||||
default:
|
||||
return SOC_RTC_FAST_CLK_SRC_INVALID;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_FAST_CLK divider. The output from the divider is passed into rtc_fast_clk MUX.
|
||||
*
|
||||
* @param divider Divider of RC_FAST_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_fast_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get RC_FAST_CLK divider
|
||||
*
|
||||
* @return Divider
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider(void)
|
||||
{
|
||||
// No divider on the target, always return divider = 1
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RC_SLOW_CLK divider
|
||||
*
|
||||
* @param divider Divider of RC_SLOW_CLK. Usually this divider is set to 1 (reg. value is 0) in bootloader stage.
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uint32_t divider)
|
||||
{
|
||||
// No divider on the target
|
||||
HAL_ASSERT(divider == 1);
|
||||
}
|
||||
|
||||
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
|
||||
/**
|
||||
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register
|
||||
*
|
||||
* Value of RTC_SLOW_CLK_CAL_REG has to be in the same format as returned by rtc_clk_cal (microseconds,
|
||||
* in Q13.19 fixed-point format).
|
||||
*
|
||||
* @param cal_value The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_cal(uint32_t cal_value)
|
||||
{
|
||||
REG_WRITE(RTC_SLOW_CLK_CAL_REG, cal_value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the calibration value of RTC_SLOW_CLK frequency from RTC storage register
|
||||
*
|
||||
* This value gets updated (i.e. rtc slow clock gets calibrated) every time RTC_SLOW_CLK source switches
|
||||
*
|
||||
* @return The calibration value of slow clock period in microseconds, in Q13.19 fixed point format
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint32_t clk_ll_rtc_slow_load_cal(void)
|
||||
{
|
||||
return REG_READ(RTC_SLOW_CLK_CAL_REG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store rtc_fix_us in RTC storage register
|
||||
*
|
||||
* @param rtc_fix_us The value used to correct the time obtained from the rtc timer when the calibration value changes
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void clk_ll_rtc_slow_store_rtc_fix_us(uint64_t rtc_fix_us)
|
||||
{
|
||||
REG_WRITE(RTC_FIX_US_LOW_REG, rtc_fix_us);
|
||||
REG_WRITE(RTC_FIX_US_HIGH_REG, rtc_fix_us >> 32);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Load the rtc_fix_ticks from RTC storage register
|
||||
*
|
||||
* @return The value used to correct the time obtained from the rtc timer when the calibration value changes
|
||||
*/
|
||||
static inline __attribute__((always_inline)) uint64_t clk_ll_rtc_slow_load_rtc_fix_us(void)
|
||||
{
|
||||
return REG_READ(RTC_FIX_US_LOW_REG) | ((uint64_t)REG_READ(RTC_FIX_US_HIGH_REG) << 32);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable/Disable the clock gate for clock output signal source
|
||||
*/
|
||||
static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
|
||||
{
|
||||
switch (clk_src)
|
||||
{
|
||||
case CLKOUT_SIG_PLL_F22M:
|
||||
PCR.ctrl_clk_out_en.clk22_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F44M:
|
||||
PCR.ctrl_clk_out_en.clk44_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F40M:
|
||||
PCR.ctrl_clk_out_en.clk_bb_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F80M:
|
||||
PCR.ctrl_clk_out_en.clk80_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_PLL_F160M:
|
||||
PCR.ctrl_clk_out_en.clk160_oen = en;
|
||||
break;
|
||||
case CLKOUT_SIG_XTAL:
|
||||
PCR.ctrl_clk_out_en.clk_xtal_oen = en;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user