mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
refactor(clk): split clock HAL into separate component
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@@ -11,7 +11,7 @@ endif()
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set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu)
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# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
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set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security esp_hal_rtc_timer)
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set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security esp_hal_rtc_timer esp_hal_clock)
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if(${target} STREQUAL "esp32c6")
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list(APPEND priv_requires hal)
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -12,7 +12,7 @@
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#include "esp_clock_output.h"
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#include "esp_check.h"
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#include "esp_rom_gpio.h"
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#include "soc/clkout_channel.h"
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#include "hal/clkout_channel.h"
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#include "hal/gpio_hal.h"
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#include "hal/clk_tree_hal.h"
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#include "hal/clk_tree_ll.h"
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@@ -233,7 +233,7 @@ esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_
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ESP_RETURN_ON_FALSE(((div_num > 0) && (div_num <= 256)), ESP_ERR_INVALID_ARG, TAG, "Divider number must be in the range of [1, 256]");
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ESP_RETURN_ON_FALSE((clkout_mapping_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
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esp_os_enter_critical(&clkout_mapping_hdl->clkout_mapping_lock);
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clk_hal_clock_output_set_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
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clk_ll_set_output_channel_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
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esp_os_exit_critical(&clkout_mapping_hdl->clkout_mapping_lock);
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return ESP_OK;
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}
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@@ -244,8 +244,8 @@ esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_
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__attribute__((constructor))
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static void esp_clock_output_pin_ctrl_init(void)
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{
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gpio_ll_set_pin_ctrl(0, CLK_OUT1, CLK_OUT1_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT2, CLK_OUT2_S);
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gpio_ll_set_pin_ctrl(0, CLK_OUT3, CLK_OUT3_S);
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clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_1);
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clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_2);
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clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_3);
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}
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#endif
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