refactor(clk): split clock HAL into separate component

This commit is contained in:
Song Ruo Jing
2026-01-31 22:32:37 +08:00
committed by morris
parent 15be2a0176
commit 89da3742b8
77 changed files with 834 additions and 800 deletions
+1 -1
View File
@@ -11,7 +11,7 @@ endif()
set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu)
# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security esp_hal_rtc_timer)
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_security esp_hal_rtc_timer esp_hal_clock)
if(${target} STREQUAL "esp32c6")
list(APPEND priv_requires hal)
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,7 +12,7 @@
#include "esp_clock_output.h"
#include "esp_check.h"
#include "esp_rom_gpio.h"
#include "soc/clkout_channel.h"
#include "hal/clkout_channel.h"
#include "hal/gpio_hal.h"
#include "hal/clk_tree_hal.h"
#include "hal/clk_tree_ll.h"
@@ -233,7 +233,7 @@ esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_
ESP_RETURN_ON_FALSE(((div_num > 0) && (div_num <= 256)), ESP_ERR_INVALID_ARG, TAG, "Divider number must be in the range of [1, 256]");
ESP_RETURN_ON_FALSE((clkout_mapping_hdl != NULL), ESP_ERR_INVALID_ARG, TAG, "Clock out mapping handle passed in is invalid");
esp_os_enter_critical(&clkout_mapping_hdl->clkout_mapping_lock);
clk_hal_clock_output_set_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
clk_ll_set_output_channel_divider(clkout_mapping_hdl->clkout_channel_hdl->channel_id, div_num);
esp_os_exit_critical(&clkout_mapping_hdl->clkout_mapping_lock);
return ESP_OK;
}
@@ -244,8 +244,8 @@ esp_err_t esp_clock_output_set_divider(esp_clock_output_mapping_handle_t clkout_
__attribute__((constructor))
static void esp_clock_output_pin_ctrl_init(void)
{
gpio_ll_set_pin_ctrl(0, CLK_OUT1, CLK_OUT1_S);
gpio_ll_set_pin_ctrl(0, CLK_OUT2, CLK_OUT2_S);
gpio_ll_set_pin_ctrl(0, CLK_OUT3, CLK_OUT3_S);
clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_1);
clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_2);
clk_ll_bind_output_channel(0, CLKOUT_CHANNEL_3);
}
#endif