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Merge branch 'feat/support_parlio_on_esp32h4_v6.0' into 'release/v6.0'

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feat(parlio): support parlio on esp32h4 (v6.0)

See merge request espressif/esp-idf!44178
This commit is contained in:
morris
2026-02-02 09:50:59 +08:00
parent c101c91019 954a7619a2
commit 88a2632a27
25 changed files with 1289 additions and 396 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+36
View File
@@ -43,6 +43,14 @@ config SOC_ETM_SUPPORTED
bool
default y
config SOC_PARLIO_SUPPORTED
bool
default y
config SOC_PARLIO_LCD_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -575,6 +583,34 @@ config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 8
config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
int
default 8
config SOC_PARLIO_TX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
bool
default y
config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PARLIO_SUPPORT_I80_LCD
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3
components/soc/esp32h4/include/soc/clk_tree_defs.h
+18
View File
@@ -461,6 +461,24 @@ typedef enum {
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_96M as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PARLIO
*/
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F96M}
/**
* @brief PARLIO clock source
*/
typedef enum {
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
PARLIO_CLK_SRC_PLL_F96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_parlio_clk_src_t;
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/include/soc/soc_caps.h
+9 -3
View File
@@ -43,7 +43,8 @@
#define SOC_TWAI_SUPPORTED 1
#define SOC_TWAI_FD_SUPPORTED 1
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347
#define SOC_PARLIO_SUPPORTED 1
#define SOC_PARLIO_LCD_SUPPORTED 1
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
@@ -325,8 +326,13 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */
#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
#define SOC_PARLIO_SUPPORT_I80_LCD 1 /*!< Support to drive I80 interfaced LCD */
/*--------------------------- SHA CAPS ---------------------------------------*/
components/soc/esp32h4/register/soc/parl_io_struct.h
+148 -148
View File
@@ -11,25 +11,25 @@ extern "C" {
#endif
/** Group: PARL_IO RX Mode Configuration */
/** Type of io_rx_mode_cfg register
/** Type of rx_mode_cfg register
* Parallel RX Sampling mode configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** io_rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
/** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
uint32_t io_rx_ext_en_sel:4;
/** io_rx_sw_en : R/W; bitpos: [25]; default: 0;
uint32_t rx_ext_en_sel:4;
/** rx_sw_en : R/W; bitpos: [25]; default: 0;
* Write 1 to enable data sampling by software.
*/
uint32_t io_rx_sw_en:1;
/** io_rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
uint32_t rx_sw_en:1;
/** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
* Write 1 to invert the external enable signal.
*/
uint32_t io_rx_ext_en_inv:1;
/** io_rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
uint32_t rx_ext_en_inv:1;
/** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
* Configures the rxd pulse sampling submode.
* 0: positive pulse start(data bit included) && positive pulse end(data bit included)
* 1: positive pulse start(data bit included) && positive pulse end (data bit excluded)
@@ -38,71 +38,71 @@ typedef union {
* 4: positive pulse start(data bit included) && length end
* 5: positive pulse start(data bit excluded) && length end
*/
uint32_t io_rx_pulse_submode_sel:3;
/** io_rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
uint32_t rx_pulse_submode_sel:3;
/** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
* Configures the rxd sampling mode.
* 0: external level enable mode
* 1: external pulse enable mode
* 2: internal software enable mode
*/
uint32_t io_rx_smp_mode_sel:2;
uint32_t rx_smp_mode_sel:2;
};
uint32_t val;
} parl_io_rx_mode_cfg_reg_t;
/** Group: PARL_IO RX Data Configuration */
/** Type of io_rx_data_cfg register
/** Type of rx_data_cfg register
* Parallel RX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_rx_bitlen : R/W; bitpos: [27:9]; default: 0;
/** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
uint32_t io_rx_bitlen:19;
/** io_rx_data_order_inv : R/W; bitpos: [28]; default: 0;
uint32_t rx_bitlen:19;
/** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from RX_FIFO to DMA.
*/
uint32_t io_rx_data_order_inv:1;
/** io_rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
uint32_t rx_data_order_inv:1;
/** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the rxd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_rx_bus_wid_sel:3;
uint32_t rx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_rx_data_cfg_reg_t;
/** Group: PARL_IO RX General Configuration */
/** Type of io_rx_genrl_cfg register
/** Type of rx_genrl_cfg register
* Parallel RX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:12;
/** io_rx_gating_en : R/W; bitpos: [12]; default: 0;
/** rx_gating_en : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
uint32_t io_rx_gating_en:1;
/** io_rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
uint32_t rx_gating_en:1;
/** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
* Configures threshold of timeout counter.
*/
uint32_t io_rx_timeout_thres:16;
/** io_rx_timeout_en : R/W; bitpos: [29]; default: 1;
uint32_t rx_timeout_thres:16;
/** rx_timeout_en : R/W; bitpos: [29]; default: 1;
* Write 1 to enable timeout function to generate error eof.
*/
uint32_t io_rx_timeout_en:1;
/** io_rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
uint32_t rx_timeout_en:1;
/** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
* Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by external enable signal.
*/
uint32_t io_rx_eof_gen_sel:1;
uint32_t rx_eof_gen_sel:1;
uint32_t reserved_31:1;
};
uint32_t val;
@@ -110,230 +110,230 @@ typedef union {
/** Group: PARL_IO RX Start Configuration */
/** Type of io_rx_start_cfg register
/** Type of rx_start_cfg register
* Parallel RX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_start : R/W; bitpos: [31]; default: 0;
/** rx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
uint32_t io_rx_start:1;
uint32_t rx_start:1;
};
uint32_t val;
} parl_io_rx_start_cfg_reg_t;
/** Group: PARL_IO TX Data Configuration */
/** Type of io_tx_data_cfg register
/** Type of tx_data_cfg register
* Parallel TX data configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** io_tx_bitlen : R/W; bitpos: [27:9]; default: 0;
/** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
uint32_t io_tx_bitlen:19;
/** io_tx_data_order_inv : R/W; bitpos: [28]; default: 0;
uint32_t tx_bitlen:19;
/** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
* Write 1 to invert bit order of one byte sent from TX_FIFO to IO data.
*/
uint32_t io_tx_data_order_inv:1;
/** io_tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
uint32_t tx_data_order_inv:1;
/** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
* Configures the txd bus width.
* 0: bus width is 1.
* 1: bus width is 2.
* 2: bus width is 4.
* 3: bus width is 8.
*/
uint32_t io_tx_bus_wid_sel:3;
uint32_t tx_bus_wid_sel:3;
};
uint32_t val;
} parl_io_tx_data_cfg_reg_t;
/** Group: PARL_IO TX Start Configuration */
/** Type of io_tx_start_cfg register
/** Type of tx_start_cfg register
* Parallel TX Start configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_start : R/W; bitpos: [31]; default: 0;
/** tx_start : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
uint32_t io_tx_start:1;
uint32_t tx_start:1;
};
uint32_t val;
} parl_io_tx_start_cfg_reg_t;
/** Group: PARL_IO TX General Configuration */
/** Type of io_tx_genrl_cfg register
/** Type of tx_genrl_cfg register
* Parallel TX general configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
/** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
*/
uint32_t io_tx_eof_gen_sel:1;
/** io_tx_idle_value : R/W; bitpos: [29:14]; default: 0;
uint32_t tx_eof_gen_sel:1;
/** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
* Configures bus value of transmitter in IDLE state.
*/
uint32_t io_tx_idle_value:16;
/** io_tx_gating_en : R/W; bitpos: [30]; default: 0;
uint32_t tx_idle_value:16;
/** tx_gating_en : R/W; bitpos: [30]; default: 0;
* Write 1 to enable the clock gating of output tx clock.
*/
uint32_t io_tx_gating_en:1;
/** io_tx_valid_output_en : R/W; bitpos: [31]; default: 0;
uint32_t tx_gating_en:1;
/** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
* Write 1 to enable the output of tx data valid signal.
*/
uint32_t io_tx_valid_output_en:1;
uint32_t tx_valid_output_en:1;
};
uint32_t val;
} parl_io_tx_genrl_cfg_reg_t;
/** Group: PARL_IO FIFO Configuration */
/** Type of io_fifo_cfg register
/** Type of fifo_cfg register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_fifo_srst : R/W; bitpos: [30]; default: 0;
/** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
uint32_t io_tx_fifo_srst:1;
/** io_rx_fifo_srst : R/W; bitpos: [31]; default: 0;
uint32_t tx_fifo_srst:1;
/** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
* Write 1 to reset async fifo in rx module.
*/
uint32_t io_rx_fifo_srst:1;
uint32_t rx_fifo_srst:1;
};
uint32_t val;
} parl_io_fifo_cfg_reg_t;
/** Group: PARL_IO Register Update Configuration */
/** Type of io_reg_update register
/** Type of reg_update register
* Parallel IO FIFO configuration register.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_rx_reg_update : WT; bitpos: [31]; default: 0;
/** rx_reg_update : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
uint32_t io_rx_reg_update:1;
uint32_t rx_reg_update:1;
};
uint32_t val;
} parl_io_reg_update_reg_t;
/** Group: PARL_IO Status */
/** Type of io_st register
/** Type of st register
* Parallel IO module status register0.
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_tx_ready : RO; bitpos: [31]; default: 0;
/** tx_ready : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
uint32_t io_tx_ready:1;
uint32_t tx_ready:1;
};
uint32_t val;
} parl_io_st_reg_t;
/** Group: PARL_IO Interrupt Configuration and Status */
/** Type of io_int_ena register
/** Type of int_ena register
* Parallel IO interrupt enable signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
/** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_ena:1;
/** io_rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
uint32_t tx_fifo_rempty_int_ena:1;
/** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
* Write 1 to enable RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_ena:1;
/** io_tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
uint32_t rx_fifo_wovf_int_ena:1;
/** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
* Write 1 to enable TX_EOF_INT.
*/
uint32_t io_tx_eof_int_ena:1;
uint32_t tx_eof_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_ena_reg_t;
/** Type of io_int_raw register
/** Type of int_raw register
* Parallel IO interrupt raw signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
/** tx_fifo_rempty_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_raw:1;
/** io_rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
uint32_t tx_fifo_rempty_int_raw:1;
/** rx_fifo_wovf_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_raw:1;
/** io_tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
uint32_t rx_fifo_wovf_int_raw:1;
/** tx_eof_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
* The raw interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_raw:1;
uint32_t tx_eof_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_raw_reg_t;
/** Type of io_int_st register
/** Type of int_st register
* Parallel IO interrupt signal status register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
/** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_st:1;
/** io_rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
uint32_t tx_fifo_rempty_int_st:1;
/** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status of RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_st:1;
/** io_tx_eof_int_st : RO; bitpos: [2]; default: 0;
uint32_t rx_fifo_wovf_int_st:1;
/** tx_eof_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status of TX_EOF_INT.
*/
uint32_t io_tx_eof_int_st:1;
uint32_t tx_eof_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} parl_io_int_st_reg_t;
/** Type of io_int_clr register
/** Type of int_clr register
* Parallel IO interrupt clear signal configuration register.
*/
typedef union {
struct {
/** io_tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
/** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
uint32_t io_tx_fifo_rempty_int_clr:1;
/** io_rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
uint32_t tx_fifo_rempty_int_clr:1;
/** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
* Write 1 to clear RX_FIFO_WOVF_INT.
*/
uint32_t io_rx_fifo_wovf_int_clr:1;
/** io_tx_eof_int_clr : WT; bitpos: [2]; default: 0;
uint32_t rx_fifo_wovf_int_clr:1;
/** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear TX_EOF_INT.
*/
uint32_t io_tx_eof_int_clr:1;
uint32_t tx_eof_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
@@ -341,183 +341,183 @@ typedef union {
/** Group: PARL_IO Rx Status0 */
/** Type of io_rx_st0 register
/** Type of rx_st0 register
* Parallel IO RX status register0
*/
typedef union {
struct {
uint32_t reserved_0:8;
/** io_rx_cnt : RO; bitpos: [12:8]; default: 0;
/** rx_cnt : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
uint32_t io_rx_cnt:5;
/** io_rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
uint32_t rx_cnt:5;
/** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current written bit number into Rx FIFO.
*/
uint32_t io_rx_fifo_wr_bit_cnt:19;
uint32_t rx_fifo_wr_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st0_reg_t;
/** Group: PARL_IO Rx Status1 */
/** Type of io_rx_st1 register
/** Type of rx_st1 register
* Parallel IO RX status register1
*/
typedef union {
struct {
uint32_t reserved_0:13;
/** io_rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
/** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
uint32_t io_rx_fifo_rd_bit_cnt:19;
uint32_t rx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_rx_st1_reg_t;
/** Group: PARL_IO Tx Status0 */
/** Type of io_tx_st0 register
/** Type of tx_st0 register
* Parallel IO TX status register0
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** io_tx_cnt : RO; bitpos: [12:6]; default: 0;
/** tx_cnt : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
uint32_t io_tx_cnt:7;
/** io_tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
uint32_t tx_cnt:7;
/** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Tx FIFO.
*/
uint32_t io_tx_fifo_rd_bit_cnt:19;
uint32_t tx_fifo_rd_bit_cnt:19;
};
uint32_t val;
} parl_io_tx_st0_reg_t;
/** Group: PARL_IO Rx Clock Configuration */
/** Type of io_rx_clk_cfg register
/** Type of rx_clk_cfg register
* Parallel IO RX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
/** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
uint32_t io_rx_clk_i_inv:1;
/** io_rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
uint32_t rx_clk_i_inv:1;
/** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Rx core clock.
*/
uint32_t io_rx_clk_o_inv:1;
uint32_t rx_clk_o_inv:1;
};
uint32_t val;
} parl_io_rx_clk_cfg_reg_t;
/** Group: PARL_IO Tx Clock Configuration */
/** Type of io_tx_clk_cfg register
/** Type of tx_clk_cfg register
* Parallel IO TX clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** io_tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
/** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
uint32_t io_tx_clk_i_inv:1;
/** io_tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
uint32_t tx_clk_i_inv:1;
/** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
* Write 1 to invert the output Tx core clock.
*/
uint32_t io_tx_clk_o_inv:1;
uint32_t tx_clk_o_inv:1;
};
uint32_t val;
} parl_io_tx_clk_cfg_reg_t;
/** Group: PARL_TX_CS Configuration */
/** Type of io_tx_cs_cfg register
/** Type of tx_cs_cfg register
* Parallel IO tx_cs_o generate configuration
*/
typedef union {
struct {
/** io_tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
/** tx_cs_stop_delay : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
uint32_t io_tx_cs_stop_delay:16;
/** io_tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
uint32_t tx_cs_stop_delay:16;
/** tx_cs_start_delay : R/W; bitpos: [31:16]; default: 0;
* configure the delay between tx_cs_o negedge and data tx start
*/
uint32_t io_tx_cs_start_delay:16;
uint32_t tx_cs_start_delay:16;
};
uint32_t val;
} parl_io_tx_cs_cfg_reg_t;
/** Group: PARL_IO Clock Configuration */
/** Type of io_clk register
/** Type of clk register
* Parallel IO clk configuration register
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** io_clk_en : R/W; bitpos: [31]; default: 0;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
uint32_t io_clk_en:1;
uint32_t clk_en:1;
};
uint32_t val;
} parl_io_clk_reg_t;
/** Group: PARL_IO Version Register */
/** Type of io_version register
/** Type of version register
* Version register.
*/
typedef union {
struct {
/** io_date : R/W; bitpos: [27:0]; default: 37786160;
/** date : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/
uint32_t io_date:28;
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} parl_io_version_reg_t;
typedef struct {
volatile parl_io_rx_mode_cfg_reg_t io_rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t io_rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t io_rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t io_rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t io_tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t io_tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t io_tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t io_fifo_cfg;
volatile parl_io_reg_update_reg_t io_reg_update;
volatile parl_io_st_reg_t io_st;
volatile parl_io_int_ena_reg_t io_int_ena;
volatile parl_io_int_raw_reg_t io_int_raw;
volatile parl_io_int_st_reg_t io_int_st;
volatile parl_io_int_clr_reg_t io_int_clr;
volatile parl_io_rx_st0_reg_t io_rx_st0;
volatile parl_io_rx_st1_reg_t io_rx_st1;
volatile parl_io_tx_st0_reg_t io_tx_st0;
volatile parl_io_rx_clk_cfg_reg_t io_rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t io_tx_clk_cfg;
volatile parl_io_tx_cs_cfg_reg_t io_tx_cs_cfg;
typedef struct parl_io_dev_t {
volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
volatile parl_io_fifo_cfg_reg_t fifo_cfg;
volatile parl_io_reg_update_reg_t reg_update;
volatile parl_io_st_reg_t st;
volatile parl_io_int_ena_reg_t int_ena;
volatile parl_io_int_raw_reg_t int_raw;
volatile parl_io_int_st_reg_t int_st;
volatile parl_io_int_clr_reg_t int_clr;
volatile parl_io_rx_st0_reg_t rx_st0;
volatile parl_io_rx_st1_reg_t rx_st1;
volatile parl_io_tx_st0_reg_t tx_st0;
volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
volatile parl_io_tx_cs_cfg_reg_t tx_cs_cfg;
uint32_t reserved_050[52];
volatile parl_io_clk_reg_t io_clk;
volatile parl_io_clk_reg_t clk;
uint32_t reserved_124[182];
volatile parl_io_version_reg_t io_version;
} parl_dev_t;
volatile parl_io_version_reg_t version;
} parl_io_dev_t;
extern parl_dev_t PARL_IO;
extern parl_io_dev_t PARL_IO;
#ifndef __cplusplus
_Static_assert(sizeof(parl_dev_t) == 0x400, "Invalid size of parl_dev_t structure");
_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32h4/register/soc/pcr_struct.h
+1 -1
View File
@@ -1178,7 +1178,7 @@ typedef union {
* Configures the clock source of Paraller IO RX
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F240M_CLK
* 2: PLL_F96M_CLK
* 3: Use the clock from chip pin
*/
uint32_t parl_clk_tx_sel:2;