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soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

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update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
This commit is contained in:
SalimTerryLi
2021-08-30 13:50:58 +08:00
parent ed8df94915
commit 874a720286
205 changed files with 1439 additions and 3252 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32/include/soc/emac_dma_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C"
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_dma_dev_s {
union {
struct {
uint32_t sw_rst : 1; /*When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit.*/
components/soc/esp32/include/soc/emac_ext_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_ext_dev_s {
union {
struct {
uint32_t div_num : 4;
components/soc/esp32/include/soc/emac_mac_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct emac_mac_dev_s {
union {
struct {
uint32_t pltf : 2; /*These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble.*/
components/soc/esp32/include/soc/i2c_struct.h
+2 -2
View File
@@ -104,8 +104,8 @@ typedef volatile struct i2c_dev_s {
} fifo_conf;
union {
struct {
uint8_t data; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint8_t reserved[3];
uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
uint32_t reserved: 24;
};
uint32_t val;
} fifo_data;
components/soc/esp32/include/soc/pcnt_struct.h
+1 -1
View File
@@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct pcnt_dev_s {
struct{
struct {
union {
struct {
uint32_t filter_thres: 10; /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
components/soc/esp32/include/soc/rmt_struct.h
+2 -4
View File
@@ -24,7 +24,7 @@ typedef volatile struct rmt_dev_s {
uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
struct{
struct {
union {
struct {
uint32_t div_cnt: 8; /*This register is used to configure the frequency divider's factor in channel0-7.*/
@@ -250,9 +250,7 @@ typedef struct rmt_item32_s {
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
};
rmt_item32_t data32[64];
} chan[8];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;
components/soc/esp32/include/soc/sdmmc_struct.h
+23 -14
View File
@@ -23,18 +23,22 @@ extern "C" {
#endif
typedef struct sdmmc_desc_s {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
};
struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
};
void* buffer1_ptr;
union {
void* buffer2_ptr;
@@ -146,8 +150,10 @@ typedef volatile struct sdmmc_dev_s {
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
struct {
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t reserved: 16;
};
uint32_t bytcnt; ///< number of bytes to be transferred
@@ -326,6 +332,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t ais: 1; ///< abnormal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
@@ -362,6 +369,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
uint32_t reserved1 : 13;
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
uint32_t reserved28: 4;
};
uint32_t val;
} cardthrctl;
@@ -378,6 +386,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t reserved21: 11;
};
uint32_t val;
} clock;
components/soc/esp32/include/soc/timer_group_struct.h
+1 -1
View File
@@ -21,7 +21,7 @@ extern "C" {
#endif
typedef volatile struct timg_dev_s {
struct{
struct {
union {
struct {
uint32_t reserved0: 10;
components/soc/esp32/include/soc/twai_struct.h
+46 -41
View File
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -60,23 +60,24 @@ typedef volatile struct twai_dev_s {
uint32_t ts: 1; /* SR.5 Transmit Status */
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
@@ -87,70 +88,70 @@ typedef volatile struct twai_dev_s {
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */
uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -158,47 +159,51 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */
uint32_t reserved3: 3; /* Internal Reserved. RXINTEN and CBP not supported */
uint32_t reserved4: 3; /* Internal Reserved. RXINTEN and CBP not supported */
uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved6: 24; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
components/soc/esp32/include/soc/uart_struct.h
+2 -2
View File
@@ -23,8 +23,8 @@ extern "C" {
typedef volatile struct uart_dev_s {
union {
struct {
uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
uint8_t reserved[3];
uint32_t rw_byte: 8; /*This register stores one byte data read by rx fifo.*/
uint32_t reserved: 24;
};
uint32_t val;
} fifo;
components/soc/esp32/include/soc/uhci_struct.h
+1 -1
View File
@@ -277,7 +277,7 @@ typedef volatile struct uhci_dev_s {
};
uint32_t val;
} quick_sent;
struct{
struct {
uint32_t w_data[2]; /*This register stores the content of short packet's dword*/
} q_data[7];
union {
components/soc/esp32c3/include/soc/apb_ctrl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;
components/soc/esp32c3/include/soc/apb_saradc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;
components/soc/esp32c3/include/soc/efuse_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/
union {
struct {
components/soc/esp32c3/include/soc/gdma_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gdma_dev_s {
struct {
union {
struct {
components/soc/esp32c3/include/soc/gpio_sd_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;
components/soc/esp32c3/include/soc/gpio_struct.h
+1 -1
View File
@@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
union {
struct {
components/soc/esp32c3/include/soc/i2c_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period : 9;
components/soc/esp32c3/include/soc/i2s_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32c3/include/soc/ledc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
components/soc/esp32c3/include/soc/rmt_struct.h
+3 -5
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /**/
union {
struct {
@@ -291,11 +291,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[48];
};
rmt_item32_t data32[48];
} chan[4];
} rmt_mem_t;
components/soc/esp32c3/include/soc/rtc_cntl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
components/soc/esp32c3/include/soc/rtc_i2c_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
components/soc/esp32c3/include/soc/sensitive_struct.h
+2 -3
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct sensitive_dev_s {
union {
struct {
uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/
@@ -959,8 +959,7 @@ typedef volatile struct {
union {
struct {
uint32_t reg_clk_en : 1; /*clk_en*/
uint32_t reserved1 : 31;
uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/
uint32_t reserved1 : 31; /*SENSITIVE_CLOCK_GATE_REG_REG*/
};
uint32_t val;
} clock_gate;
components/soc/esp32c3/include/soc/spi_mem_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
components/soc/esp32c3/include/soc/spi_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
components/soc/esp32c3/include/soc/syscon_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t apb_ctrl_pre_div_cnt: 10;
components/soc/esp32c3/include/soc/system_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct system_dev_s {
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
components/soc/esp32c3/include/soc/systimer_struct.h
+10
View File
@@ -88,6 +88,7 @@ typedef union {
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
@@ -102,6 +103,7 @@ typedef struct {
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -126,6 +128,7 @@ typedef struct {
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -172,6 +175,7 @@ typedef struct {
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -195,6 +199,7 @@ typedef union {
* timer comp load value
*/
uint32_t timer_comp_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp_load_reg_t;
@@ -208,6 +213,7 @@ typedef union {
* timer unit load value
*/
uint32_t timer_unit_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit_load_reg_t;
@@ -230,6 +236,7 @@ typedef union {
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@@ -251,6 +258,7 @@ typedef union {
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@@ -272,6 +280,7 @@ typedef union {
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
@@ -293,6 +302,7 @@ typedef union {
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_st_reg_t;
components/soc/esp32c3/include/soc/twai_struct.h
+47 -41
View File
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved1: 1; /* Internal Reserved */
uint32_t reserved13: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
components/soc/esp32c3/include/soc/uart_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte; /*a*/
components/soc/esp32c3/include/soc/uhci_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct usb_serial_jtag_dev_s {
union {
struct {
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
components/soc/esp32h2/include/soc/apb_ctrl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/apb_saradc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;
components/soc/esp32h2/include/soc/efuse_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/
union {
struct {
components/soc/esp32h2/include/soc/gdma_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gdma_dev_s {
struct {
union {
struct {
components/soc/esp32h2/include/soc/gpio_sd_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;
components/soc/esp32h2/include/soc/gpio_struct.h
+1 -1
View File
@@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
union {
struct {
components/soc/esp32h2/include/soc/i2c_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period : 9;
components/soc/esp32h2/include/soc/i2s_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/ledc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
components/soc/esp32h2/include/soc/rmt_struct.h
+3 -5
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /**/
union {
struct {
@@ -291,11 +291,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[48];
};
rmt_item32_t data32[48];
} chan[4];
} rmt_mem_t;
components/soc/esp32h2/include/soc/rtc_cntl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
components/soc/esp32h2/include/soc/rtc_i2c_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
components/soc/esp32h2/include/soc/sensitive_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct sensitive_dev_s {
union {
struct {
uint32_t reg_rom_table_lock : 1; /*rom_table_lock*/
components/soc/esp32h2/include/soc/spi_mem_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
components/soc/esp32h2/include/soc/spi_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
components/soc/esp32h2/include/soc/syscon_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32h2/include/soc/system_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct system_dev_s {
union {
struct {
uint32_t reserved0 : 6; /*reserved*/
components/soc/esp32h2/include/soc/systimer_struct.h
+10
View File
@@ -88,6 +88,7 @@ typedef union {
* update timer_unit0
*/
uint32_t timer_unit_update: 1;
uint32_t reserved31: 1;
};
uint32_t val;
} systimer_unit_op_reg_t;
@@ -102,6 +103,7 @@ typedef struct {
* timer unit load high 32 bit
*/
uint32_t timer_unit_load_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -126,6 +128,7 @@ typedef struct {
* timer target high 32 bit
*/
uint32_t timer_target_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -172,6 +175,7 @@ typedef struct {
* timer read value high 20bit
*/
uint32_t timer_unit_value_hi: 20;
uint32_t reserved20: 12;
};
uint32_t val;
} hi;
@@ -195,6 +199,7 @@ typedef union {
* timer comp load value
*/
uint32_t timer_comp_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_comp_load_reg_t;
@@ -208,6 +213,7 @@ typedef union {
* timer unit load value
*/
uint32_t timer_unit_load: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} systimer_unit_load_reg_t;
@@ -230,6 +236,7 @@ typedef union {
* interupt2 enable
*/
uint32_t target2_int_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@@ -251,6 +258,7 @@ typedef union {
* interupt2 raw
*/
uint32_t target2_int_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@@ -272,6 +280,7 @@ typedef union {
* interupt2 clear
*/
uint32_t target2_int_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
@@ -293,6 +302,7 @@ typedef union {
* reg_target2_int_st
*/
uint32_t target2_int_st: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_st_reg_t;
components/soc/esp32h2/include/soc/twai_struct.h
+47 -41
View File
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -61,97 +61,99 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
uint32_t reserved1: 1; /* Internal Reserved */
uint32_t reserved13: 1; /* Internal Reserved */
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -159,45 +161,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
components/soc/esp32h2/include/soc/uart_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte; /*a*/
components/soc/esp32h2/include/soc/uhci_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
typedef volatile struct usb_serial_jtag_dev_s {
union {
struct {
uint32_t rdwr_byte : 8; /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
components/soc/esp32s2/include/soc/apb_ctrl_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;
components/soc/esp32s2/include/soc/apb_saradc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;
components/soc/esp32s2/include/soc/cp_dma_struct.h
+6
View File
@@ -69,6 +69,7 @@ typedef union {
* This is the interrupt raw bit. Triggered when crc calculation is done.
*/
uint32_t dma_crc_done_int_raw: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_raw_reg_t;
@@ -123,6 +124,7 @@ typedef union {
* cp_crc_done_int_ena is set to 1.
*/
uint32_t dma_crc_done_int_st: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_st_reg_t;
@@ -168,6 +170,7 @@ typedef union {
* This is the interrupt enable bit for cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_ena: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_ena_reg_t;
@@ -213,6 +216,7 @@ typedef union {
* Set this bit to clear cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_clr: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_clr_reg_t;
@@ -491,6 +495,7 @@ typedef union {
* Copy DMA FIFO empty signal.
*/
uint32_t dma_fifo_empty: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_in_st_reg_t;
@@ -516,6 +521,7 @@ typedef union {
* Copy DMA FIFO full signal.
*/
uint32_t dma_fifo_full: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_out_st_reg_t;
components/soc/esp32s2/include/soc/dedic_gpio_struct.h
+12
View File
@@ -31,6 +31,7 @@ typedef union {
* gpio.
*/
uint32_t gpio_out_drt_vlaue: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_drt_reg_t;
@@ -49,6 +50,7 @@ typedef union {
* channel's output would be masked.
*/
uint32_t gpio_out_msk: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_msk_reg_t;
@@ -98,6 +100,7 @@ typedef union {
* clear output value; 3: inverse output value.
*/
uint32_t gpio_out_idv_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_idv_reg_t;
@@ -147,6 +150,7 @@ typedef union {
* select CPU instructors.
*/
uint32_t gpio_out_cpu_sel7: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_cpu_reg_t;
@@ -196,6 +200,7 @@ typedef union {
* 3: three clock delay.
*/
uint32_t gpio_in_dly_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_in_dly_reg_t;
@@ -285,6 +290,7 @@ typedef union {
* 6/7: falling and raising edge trigger.
*/
uint32_t gpio_intr_mode_ch7: 3;
uint32_t reserved24: 8;
};
uint32_t val;
} dedic_gpio_intr_rcgn_reg_t;
@@ -301,6 +307,7 @@ typedef union {
* DEDIC_GPIO_OUT_IDV_REG.
*/
uint32_t gpio_out_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_scan_reg_t;
@@ -314,6 +321,7 @@ typedef union {
* gpio in value after configured by DEDIC_GPIO_IN_DLY_REG.
*/
uint32_t gpio_in_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_in_scan_reg_t;
@@ -365,6 +373,7 @@ typedef union {
* change configured by DEDIC_GPIO_INTR_RCGN_REG.
*/
uint32_t gpio7_int_raw: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_raw_reg_t;
@@ -406,6 +415,7 @@ typedef union {
* This enable bit for reg_gpio7_int_st register.
*/
uint32_t gpio7_int_ena: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_rls_reg_t;
@@ -447,6 +457,7 @@ typedef union {
* This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1.
*/
uint32_t gpio7_int_st: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_st_reg_t;
@@ -488,6 +499,7 @@ typedef union {
* Set this bit to clear the reg_gpio7_int_raw interrupt.
*/
uint32_t gpio7_int_clr: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_clr_reg_t;
components/soc/esp32s2/include/soc/efuse_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /**/
union {
struct {
components/soc/esp32s2/include/soc/gpio_sd_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;
components/soc/esp32s2/include/soc/gpio_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/
components/soc/esp32s2/include/soc/i2c_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period: 14;
components/soc/esp32s2/include/soc/i2s_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
union {
components/soc/esp32s2/include/soc/ledc_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
components/soc/esp32s2/include/soc/rmt_struct.h
+3 -5
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
struct {
union {
@@ -300,11 +300,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
};
rmt_item32_t data32[64];
} chan[4];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;
components/soc/esp32s2/include/soc/rtc_cntl_struct.h
+1 -1
View File
@@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
components/soc/esp32s2/include/soc/rtc_i2c_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
components/soc/esp32s2/include/soc/rtc_io_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0: 10;
components/soc/esp32s2/include/soc/sens_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sens_dev_s {
union {
struct {
uint32_t sar1_clk_div: 8; /*clock divider*/
components/soc/esp32s2/include/soc/syscon_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t pre_div: 10;
components/soc/esp32s2/include/soc/systimer_struct.h
+4
View File
@@ -91,6 +91,7 @@ typedef union {
* system timer accumulation step when using PLL
*/
uint32_t timer_pll_step: 10;
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_step_reg_t;
@@ -201,6 +202,7 @@ typedef union {
* system timer target2 interrupt enable
*/
uint32_t systimer_int2_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@@ -222,6 +224,7 @@ typedef union {
* system timer target2 interrupt raw
*/
uint32_t systimer_int2_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@@ -243,6 +246,7 @@ typedef union {
* system timer target2 interrupt clear
*/
uint32_t systimer_int2_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;
components/soc/esp32s2/include/soc/twai_struct.h
+46 -40
View File
@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -61,37 +61,39 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 14; /* BTR0[13:0] Baud Rate Prescaler */
@@ -99,58 +101,58 @@ typedef volatile struct twai_dev_s {
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -158,45 +160,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
components/soc/esp32s2/include/soc/uart_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/
components/soc/esp32s2/include/soc/uhci_struct.h
+1 -1
View File
@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t in_rst: 1;
components/soc/esp32s2/include/soc/usb_wrap_struct.h
+1
View File
@@ -153,6 +153,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;
components/soc/esp32s2/include/soc/usbh_struct.h
+1 -1
View File
@@ -830,7 +830,7 @@ typedef union {
uint32_t bbleerr: 1;
uint32_t nakintrpt: 1;
uint32_t nyetintrpt: 1;
uint32_t reserved16: 16;
uint32_t reserved15: 17;
};
uint32_t val;
} usb_diepint_reg_t;
components/soc/esp32s3/include/soc/apb_ctrl_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div : 10;
components/soc/esp32s3/include/soc/apb_saradc_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force : 1;
components/soc/esp32s3/include/soc/assist_debug_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct assist_debug_dev_s {
union {
struct {
uint32_t core_0_area_dram0_0_rd : 1;
components/soc/esp32s3/include/soc/efuse_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0;
uint32_t pgm_data1;
uint32_t pgm_data2;
components/soc/esp32s3/include/soc/extmem_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct extmem_dev_s {
union {
struct {
uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
components/soc/esp32s3/include/soc/gdma_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gdma_dev_s {
struct {
struct {
union {
components/soc/esp32s3/include/soc/gpio_sd_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty : 8;
components/soc/esp32s3/include/soc/gpio_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select;
uint32_t out;
uint32_t out_w1ts;
components/soc/esp32s3/include/soc/hinf_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct hinf_dev_s {
union {
struct {
uint32_t user_id_fn1: 16;
components/soc/esp32s3/include/soc/host_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct host_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32s3/include/soc/i2s_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32s3/include/soc/interrupt_core0_struct.h
+1 -1
View File
@@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct interrupt_core0_dev_s {
union {
struct {
uint32_t core0_mac_intr_map: 5;
components/soc/esp32s3/include/soc/interrupt_core1_struct.h
+1 -1
View File
@@ -18,7 +18,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct interrupt_core1_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
components/soc/esp32s3/include/soc/interrupt_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct interrupt_dev_s {
} interrupt_dev_t;
extern interrupt_dev_t INTERRUPT;
#ifdef __cplusplus
components/soc/esp32s3/include/soc/ledc_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {
components/soc/esp32s3/include/soc/peri_backup_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct peri_backup_dev_s {
union {
struct {
uint32_t reg_peri_backup_flow_err : 3;
components/soc/esp32s3/include/soc/rmt_struct.h
+1 -3
View File
@@ -1103,9 +1103,7 @@ typedef struct {
typedef struct {
struct {
union {
volatile rmt_item32_t data32[48];
};
volatile rmt_item32_t data32[48];
} chan[8];
} rmt_mem_t;
components/soc/esp32s3/include/soc/rtc_cntl_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0 : 2; /*{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
components/soc/esp32s3/include/soc/rtc_io_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0 : 10;
components/soc/esp32s3/include/soc/sdmmc_struct.h
+23 -15
View File
@@ -21,18 +21,22 @@ extern "C" {
#endif
typedef struct sdmmc_desc_s {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
struct {
uint32_t reserved1: 1;
uint32_t disable_int_on_completion: 1;
uint32_t last_descriptor: 1;
uint32_t first_descriptor: 1;
uint32_t second_address_chained: 1;
uint32_t end_of_ring: 1;
uint32_t reserved2: 24;
uint32_t card_error_summary: 1;
uint32_t owned_by_idmac: 1;
};
struct {
uint32_t buffer1_size: 13;
uint32_t buffer2_size: 13;
uint32_t reserved3: 6;
};
void* buffer1_ptr;
union {
void* buffer2_ptr;
@@ -144,8 +148,10 @@ typedef volatile struct sdmmc_dev_s {
uint32_t val;
} ctype;
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t : 16;
struct {
uint32_t blksiz: 16; ///< block size, default 0x200
uint32_t reserved: 16;
};
uint32_t bytcnt; ///< number of bytes to be transferred
@@ -324,6 +330,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t ces: 1; ///< card error summary
uint32_t reserved2: 2;
uint32_t nis: 1; ///< normal interrupt summary
uint32_t ais: 1; ///< abnormal interrupt summary
uint32_t fbe_code: 3; ///< code of fatal bus error
uint32_t fsm: 4; ///< DMAC FSM state
uint32_t reserved3: 15;
@@ -359,7 +366,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
uint32_t reserved1 : 13;
uint32_t card_threshold : 12; ///< threshold value for reads/writes, in bytes
uint32_t card_threshold : 16; ///< threshold value for reads/writes, in bytes
};
uint32_t val;
} cardthrctl;
@@ -378,6 +385,7 @@ typedef volatile struct sdmmc_dev_s {
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
uint32_t reserved1 : 2;
uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
uint32_t reserved24: 8;
};
uint32_t val;
} clock;
components/soc/esp32s3/include/soc/sens_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sens_dev_s {
union {
struct {
uint32_t sar1_clk_div : 8; /*clock divider*/
components/soc/esp32s3/include/soc/sensitive_struct.h
+1 -1
View File
@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sensitive_dev_s {
union {
struct {
uint32_t cache_dataarray_connect_lock : 1;
components/soc/esp32s3/include/soc/slc_reg.h
-1912
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