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feat(efuse): Update efuse table for ESP32-H4

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This commit is contained in:
Konstantin Kondrashov
2026-04-01 16:15:45 +03:00
parent 1c43172477
commit 8701705ec3
14 changed files with 1972 additions and 408 deletions
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components/efuse/esp32h4/esp_efuse_table.c
+767 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 00c61e1122b40bab1153117e162a713c
// md5_digest_table 4d334deda739743601735f09078a9fd5
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -79,6 +79,14 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
};
static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_EN[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PVT_GLITCH_EN,
};
static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_MODE[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PVT_GLITCH_MODE,
};
static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
{EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
};
@@ -135,6 +143,10 @@ static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_SHA384_EN[] = {
{EFUSE_BLK0, 14, 1}, // [] wr_dis of SECURE_BOOT_SHA384_EN,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
{EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
};
@@ -231,10 +243,170 @@ static const esp_efuse_desc_t WR_DIS_FLASH_LDO_POWER_SEL[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_LDO_POWER_SEL,
};
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR,
};
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
};
static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_TEMP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP,
};
static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
};
static const esp_efuse_desc_t WR_DIS_PVT_DBIAS[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_DBIAS,
};
static const esp_efuse_desc_t WR_DIS_ADJUST_1V2[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ADJUST_1V2,
};
static const esp_efuse_desc_t WR_DIS_ADJUST_1V8[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ADJUST_1V8,
};
static const esp_efuse_desc_t WR_DIS_ACTIVE_DCDC_1V25[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_DCDC_1V25,
};
static const esp_efuse_desc_t WR_DIS_ACTIVE_DCDC_1V35[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_DCDC_1V35,
};
static const esp_efuse_desc_t WR_DIS_SLP_DCDC[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of SLP_DCDC,
};
static const esp_efuse_desc_t WR_DIS_LSLP_HP_DRVB[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DRVB,
};
static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS,
};
static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP_CALIB,
};
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
};
static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
};
static const esp_efuse_desc_t WR_DIS_OCODE[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
};
static const esp_efuse_desc_t WR_DIS_DCDC_OCODE[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of DCDC_OCODE,
};
static const esp_efuse_desc_t WR_DIS_VDD_3V4_DOUT[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of VDD_3V4_DOUT,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_INITCODE_DIFF_1P8_3P3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of INITCODE_DIFF_1P8_3P3,
};
static const esp_efuse_desc_t WR_DIS_HI_DOUT_DIFF_1P8_3P3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of HI_DOUT_DIFF_1P8_3P3,
};
static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
{EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
};
@@ -275,6 +447,14 @@ static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS,
};
static const esp_efuse_desc_t WR_DIS_USB_OTG_FS_EXCHG_PINS[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_OTG_FS_EXCHG_PINS,
};
static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_PHY_SEL,
};
static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
{EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG,
};
@@ -569,6 +749,166 @@ static const esp_efuse_desc_t FLASH_LDO_POWER_SEL[] = {
{EFUSE_BLK1, 113, 1}, // [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 4}, // [] Minor chip version,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 118, 2}, // [] Major chip version,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 120, 1}, // [] Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 121, 1}, // [] Disables check of blk version major,
};
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 122, 3}, // [] BLK_VERSION_MINOR of BLOCK2,
};
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 125, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
};
static const esp_efuse_desc_t FLASH_CAP[] = {
{EFUSE_BLK1, 127, 3}, // [] Flash capacity,
};
static const esp_efuse_desc_t FLASH_VENDOR[] = {
{EFUSE_BLK1, 130, 3}, // [] Flash vendor,
};
static const esp_efuse_desc_t PSRAM_CAP[] = {
{EFUSE_BLK1, 133, 3}, // [] Psram capacity,
};
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
{EFUSE_BLK1, 136, 2}, // [] Psram vendor,
};
static const esp_efuse_desc_t TEMP[] = {
{EFUSE_BLK1, 138, 2}, // [] Temp (die embedded inside),
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 140, 3}, // [] Package version,
};
static const esp_efuse_desc_t PVT_DBIAS[] = {
{EFUSE_BLK1, 143, 5}, // [] PVT DBIAS,
};
static const esp_efuse_desc_t ADJUST_1V2[] = {
{EFUSE_BLK1, 148, 4}, // [] SPI LDO adjust of 1.2v,
};
static const esp_efuse_desc_t ADJUST_1V8[] = {
{EFUSE_BLK1, 152, 4}, // [] SPI LDO adjust of 1.8v,
};
static const esp_efuse_desc_t ACTIVE_DCDC_1V25[] = {
{EFUSE_BLK1, 156, 4}, // [] DCDC-DCDC DBIAS of 1.25v,
};
static const esp_efuse_desc_t ACTIVE_DCDC_1V35[] = {
{EFUSE_BLK1, 160, 4}, // [] DCDC-DCDC DBIAS of 1.35v,
};
static const esp_efuse_desc_t SLP_DCDC[] = {
{EFUSE_BLK1, 164, 5}, // [] DCDC DBIAS in sleep,
};
static const esp_efuse_desc_t LSLP_HP_DRVB[] = {
{EFUSE_BLK1, 169, 5}, // [] HP DRVB in light sleep,
};
static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
{EFUSE_BLK1, 174, 2}, // [] LP DBIAS in deep sleep,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
{EFUSE_BLK1, 176, 10}, // [] Temperature calibration data,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
};
static const esp_efuse_desc_t OCODE[] = {
{EFUSE_BLK2, 128, 8}, // [] ADC OCode,
};
static const esp_efuse_desc_t DCDC_OCODE[] = {
{EFUSE_BLK2, 136, 8}, // [] DCDC OCode,
};
static const esp_efuse_desc_t VDD_3V4_DOUT[] = {
{EFUSE_BLK2, 144, 10}, // [] ADC dout of vdd 3.4v,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
{EFUSE_BLK2, 154, 9}, // [] Average initcode of ADC1 atten0,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
{EFUSE_BLK2, 163, 9}, // [] Average initcode of ADC1 atten1,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
{EFUSE_BLK2, 172, 9}, // [] Average initcode of ADC1 atten2,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
{EFUSE_BLK2, 181, 9}, // [] Average initcode of ADC1 atten3,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
{EFUSE_BLK2, 190, 9}, // [] HI dout of ADC1 atten0,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
{EFUSE_BLK2, 199, 9}, // [] HI dout of ADC1 atten1,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
{EFUSE_BLK2, 208, 9}, // [] HI dout of ADC1 atten2,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
{EFUSE_BLK2, 217, 9}, // [] HI dout of ADC1 atten3,
};
static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 226, 3}, // [] Gap between ADC1 CH0 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 229, 3}, // [] Gap between ADC1 CH1 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 232, 3}, // [] Gap between ADC1 CH2 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 235, 3}, // [] Gap between ADC1 CH3 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 238, 3}, // [] Gap between ADC1 CH4 and average initcode,
};
static const esp_efuse_desc_t INITCODE_DIFF_1P8_3P3[] = {
{EFUSE_BLK2, 241, 5}, // [] Initcode diff between IO LDO 1.8v and 3.3v,
};
static const esp_efuse_desc_t HI_DOUT_DIFF_1P8_3P3[] = {
{EFUSE_BLK2, 246, 5}, // [] HI dout diff between IO LDO 1.8v and 3.3v,
};
static const esp_efuse_desc_t USER_DATA[] = {
{EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
};
@@ -689,6 +1029,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[] = {
&WR_DIS_PVT_GLITCH_EN[0], // [] wr_dis of PVT_GLITCH_EN
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[] = {
&WR_DIS_PVT_GLITCH_MODE[0], // [] wr_dis of PVT_GLITCH_MODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
&WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT
NULL
@@ -759,6 +1109,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[] = {
&WR_DIS_SECURE_BOOT_SHA384_EN[0], // [] wr_dis of SECURE_BOOT_SHA384_EN
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
&WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
NULL
@@ -879,11 +1234,211 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
&WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
&WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
&WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
&WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
&WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
&WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
&WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
&WR_DIS_TEMP[0], // [] wr_dis of TEMP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
&WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[] = {
&WR_DIS_PVT_DBIAS[0], // [] wr_dis of PVT_DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V2[] = {
&WR_DIS_ADJUST_1V2[0], // [] wr_dis of ADJUST_1V2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V8[] = {
&WR_DIS_ADJUST_1V8[0], // [] wr_dis of ADJUST_1V8
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V25[] = {
&WR_DIS_ACTIVE_DCDC_1V25[0], // [] wr_dis of ACTIVE_DCDC_1V25
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V35[] = {
&WR_DIS_ACTIVE_DCDC_1V35[0], // [] wr_dis of ACTIVE_DCDC_1V35
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SLP_DCDC[] = {
&WR_DIS_SLP_DCDC[0], // [] wr_dis of SLP_DCDC
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DRVB[] = {
&WR_DIS_LSLP_HP_DRVB[0], // [] wr_dis of LSLP_HP_DRVB
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
&WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
&WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
&WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
&WR_DIS_OCODE[0], // [] wr_dis of OCODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DCDC_OCODE[] = {
&WR_DIS_DCDC_OCODE[0], // [] wr_dis of DCDC_OCODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_3V4_DOUT[] = {
&WR_DIS_VDD_3V4_DOUT[0], // [] wr_dis of VDD_3V4_DOUT
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_INITCODE_DIFF_1P8_3P3[] = {
&WR_DIS_INITCODE_DIFF_1P8_3P3[0], // [] wr_dis of INITCODE_DIFF_1P8_3P3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HI_DOUT_DIFF_1P8_3P3[] = {
&WR_DIS_HI_DOUT_DIFF_1P8_3P3[0], // [] wr_dis of HI_DOUT_DIFF_1P8_3P3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
&WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
NULL
@@ -934,6 +1489,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG_FS_EXCHG_PINS[] = {
&WR_DIS_USB_OTG_FS_EXCHG_PINS[0], // [] wr_dis of USB_OTG_FS_EXCHG_PINS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = {
&WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
&WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG
NULL
@@ -1300,6 +1865,206 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // [] Minor chip version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // [] Major chip version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
&FLASH_CAP[0], // [] Flash capacity
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
&FLASH_VENDOR[0], // [] Flash vendor
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
&PSRAM_CAP[0], // [] Psram capacity
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
&PSRAM_VENDOR[0], // [] Psram vendor
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
&TEMP[0], // [] Temp (die embedded inside)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // [] Package version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[] = {
&PVT_DBIAS[0], // [] PVT DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V2[] = {
&ADJUST_1V2[0], // [] SPI LDO adjust of 1.2v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V8[] = {
&ADJUST_1V8[0], // [] SPI LDO adjust of 1.8v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V25[] = {
&ACTIVE_DCDC_1V25[0], // [] DCDC-DCDC DBIAS of 1.25v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V35[] = {
&ACTIVE_DCDC_1V35[0], // [] DCDC-DCDC DBIAS of 1.35v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SLP_DCDC[] = {
&SLP_DCDC[0], // [] DCDC DBIAS in sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DRVB[] = {
&LSLP_HP_DRVB[0], // [] HP DRVB in light sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
&DSLP_LP_DBIAS[0], // [] LP DBIAS in deep sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
&TEMP_CALIB[0], // [] Temperature calibration data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
&OCODE[0], // [] ADC OCode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DCDC_OCODE[] = {
&DCDC_OCODE[0], // [] DCDC OCode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_VDD_3V4_DOUT[] = {
&VDD_3V4_DOUT[0], // [] ADC dout of vdd 3.4v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
&ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
&ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
&ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
&ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
&ADC1_HI_DOUT_ATTEN0[0], // [] HI dout of ADC1 atten0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
&ADC1_HI_DOUT_ATTEN1[0], // [] HI dout of ADC1 atten1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
&ADC1_HI_DOUT_ATTEN2[0], // [] HI dout of ADC1 atten2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
&ADC1_HI_DOUT_ATTEN3[0], // [] HI dout of ADC1 atten3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH4 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_INITCODE_DIFF_1P8_3P3[] = {
&INITCODE_DIFF_1P8_3P3[0], // [] Initcode diff between IO LDO 1.8v and 3.3v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_HI_DOUT_DIFF_1P8_3P3[] = {
&HI_DOUT_DIFF_1P8_3P3[0], // [] HI dout diff between IO LDO 1.8v and 3.3v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
&USER_DATA[0], // [BLOCK_USR_DATA] User data
NULL
components/efuse/esp32h4/esp_efuse_table.csv
+86 -1
View File
@@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: 7bc342bad0952907e1db21112d258c6b
# This file was generated by regtools.py based on the efuses.yaml file with the version: 6c3ca4b9e6c9ee71a1a0627fa77a905a
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@@ -27,6 +27,8 @@ WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_EN
WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_MODE
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
@@ -41,6 +43,7 @@ WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
WR_DIS.SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 14, 1, [] wr_dis of SECURE_BOOT_SHA384_EN
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
@@ -65,7 +68,47 @@ WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 20, 1, [] wr_dis
WR_DIS.PVT_GLITCH_CHARGE_RESET, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_GLITCH_CHARGE_RESET
WR_DIS.VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 20, 1, [] wr_dis of VDD_SPI_LDO_ADJUST
WR_DIS.FLASH_LDO_POWER_SEL, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_LDO_POWER_SEL
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.PVT_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_DBIAS
WR_DIS.ADJUST_1V2, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V2
WR_DIS.ADJUST_1V8, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V8
WR_DIS.ACTIVE_DCDC_1V25, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V25
WR_DIS.ACTIVE_DCDC_1V35, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V35
WR_DIS.SLP_DCDC, EFUSE_BLK0, 20, 1, [] wr_dis of SLP_DCDC
WR_DIS.LSLP_HP_DRVB, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DRVB
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP_CALIB
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
WR_DIS.DCDC_OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of DCDC_OCODE
WR_DIS.VDD_3V4_DOUT, EFUSE_BLK0, 21, 1, [] wr_dis of VDD_3V4_DOUT
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.INITCODE_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of INITCODE_DIFF_1P8_3P3
WR_DIS.HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of HI_DOUT_DIFF_1P8_3P3
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -76,6 +119,8 @@ WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.K
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
WR_DIS.USB_OTG_FS_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG_FS_EXCHG_PINS
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
@@ -154,6 +199,46 @@ HYS_EN_PAD, EFUSE_BLK1, 102, 1, [] Repres
PVT_GLITCH_CHARGE_RESET, EFUSE_BLK1, 103, 1, [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset
VDD_SPI_LDO_ADJUST, EFUSE_BLK1, 105, 8, [] Represents configuration of FLASH LDO mode and voltage.
FLASH_LDO_POWER_SEL, EFUSE_BLK1, 113, 1, [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version
WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 1, [] Disables check of blk version major
BLK_VERSION_MINOR, EFUSE_BLK1, 122, 3, [] BLK_VERSION_MINOR of BLOCK2
BLK_VERSION_MAJOR, EFUSE_BLK1, 125, 2, [] BLK_VERSION_MAJOR of BLOCK2
FLASH_CAP, EFUSE_BLK1, 127, 3, [] Flash capacity
FLASH_VENDOR, EFUSE_BLK1, 130, 3, [] Flash vendor
PSRAM_CAP, EFUSE_BLK1, 133, 3, [] Psram capacity
PSRAM_VENDOR, EFUSE_BLK1, 136, 2, [] Psram vendor
TEMP, EFUSE_BLK1, 138, 2, [] Temp (die embedded inside)
PKG_VERSION, EFUSE_BLK1, 140, 3, [] Package version
PVT_DBIAS, EFUSE_BLK1, 143, 5, [] PVT DBIAS
ADJUST_1V2, EFUSE_BLK1, 148, 4, [] SPI LDO adjust of 1.2v
ADJUST_1V8, EFUSE_BLK1, 152, 4, [] SPI LDO adjust of 1.8v
ACTIVE_DCDC_1V25, EFUSE_BLK1, 156, 4, [] DCDC-DCDC DBIAS of 1.25v
ACTIVE_DCDC_1V35, EFUSE_BLK1, 160, 4, [] DCDC-DCDC DBIAS of 1.35v
SLP_DCDC, EFUSE_BLK1, 164, 5, [] DCDC DBIAS in sleep
LSLP_HP_DRVB, EFUSE_BLK1, 169, 5, [] HP DRVB in light sleep
DSLP_LP_DBIAS, EFUSE_BLK1, 174, 2, [] LP DBIAS in deep sleep
TEMP_CALIB, EFUSE_BLK1, 176, 10, [] Temperature calibration data
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
OCODE, EFUSE_BLK2, 128, 8, [] ADC OCode
DCDC_OCODE, EFUSE_BLK2, 136, 8, [] DCDC OCode
VDD_3V4_DOUT, EFUSE_BLK2, 144, 10, [] ADC dout of vdd 3.4v
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 154, 9, [] Average initcode of ADC1 atten0
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 163, 9, [] Average initcode of ADC1 atten1
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 172, 9, [] Average initcode of ADC1 atten2
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 181, 9, [] Average initcode of ADC1 atten3
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 190, 9, [] HI dout of ADC1 atten0
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 199, 9, [] HI dout of ADC1 atten1
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 208, 9, [] HI dout of ADC1 atten2
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 217, 9, [] HI dout of ADC1 atten3
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 226, 3, [] Gap between ADC1 CH0 and average initcode
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 3, [] Gap between ADC1 CH1 and average initcode
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 232, 3, [] Gap between ADC1 CH2 and average initcode
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 235, 3, [] Gap between ADC1 CH3 and average initcode
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 238, 3, [] Gap between ADC1 CH4 and average initcode
INITCODE_DIFF_1P8_3P3, EFUSE_BLK2, 241, 5, [] Initcode diff between IO LDO 1.8v and 3.3v
HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK2, 246, 5, [] HI dout diff between IO LDO 1.8v and 3.3v
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
Can't render this file because it contains an unexpected character in line 8 and column 53.
components/efuse/esp32h4/include/esp_efuse_chip.h
+13 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -62,16 +62,25 @@ typedef enum {
*/
typedef enum {
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_RESERVED = 2, /**< Reserved (Used as a place holder)*/
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (P256) (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< Flash encryption key (XTS_AES_256_KEY_1) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< Flash encryption key (XTS_AES_256_KEY_2) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Keep for compatibility although H4 has no DS peripheral */
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key (P192) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key (P384 low) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key (P384 high) */
ESP_EFUSE_KEY_PURPOSE_MAX = 32, /**< MAX PURPOSE */
} esp_efuse_purpose_t;
components/efuse/esp32h4/include/esp_efuse_table.h
+87 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 00c61e1122b40bab1153117e162a713c
// md5_digest_table 4d334deda739743601735f09078a9fd5
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -33,6 +33,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
@@ -53,6 +55,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
@@ -78,7 +81,47 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_LDO_ADJUST[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V8[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V25[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V35[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SLP_DCDC[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DRVB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DCDC_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_3V4_DOUT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_INITCODE_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HI_DOUT_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -99,6 +142,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG_FS_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
@@ -185,6 +230,46 @@ extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V8[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V25[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V35[];
extern const esp_efuse_desc_t* ESP_EFUSE_SLP_DCDC[];
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DRVB[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_3V4_DOUT[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_INITCODE_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_HI_DOUT_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];