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Merge branch 'fix/esp32p4_rev3_hardware_issue_workarounds_v6.0' into 'release/v6.0'

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fix(esp_hw_support): esp32p4 eco5 hardware issues workaround (v6.0)

See merge request espressif/esp-idf!42941
This commit is contained in:
Jiang Jiang Jian
2025-11-14 16:47:24 +08:00
parent 1045fb094b 5eff18eec2
commit 86d09a29c6
32 changed files with 406 additions and 51 deletions
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components/hal/esp32p4/include/hal/lp_clkrst_ll.h
+35
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@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 LP_CLKRST register operations
#pragma once
#include <stdbool.h>
#include <stdlib.h>
#include "soc/soc.h"
#include "soc/lp_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Select CPU reset vector
* @param boot_from_lp_ram
* true: boot from LP TCM RAM: 0x50108000
* false: boot from HP TCM ROM: 0x4FC00000
*/
__attribute__((always_inline))
static inline void lp_clkrst_ll_boot_from_lp_ram(bool boot_from_lp_ram)
{
LP_AON_CLKRST.hpcpu_reset_ctrl0.hpcore0_stat_vector_sel = !boot_from_lp_ram;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32p4/include/hal/lp_sys_ll.h
+22 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,6 +13,7 @@
#include "soc/soc.h"
#include "soc/lp_system_struct.h"
#include "hal/misc.h"
#include "hal/config.h"
#include "esp32p4/rom/rtc.h"
@@ -20,6 +21,10 @@
extern "C" {
#endif
#define MEM_AUX_SHUTDOWN BIT(0)
#define MEM_AUX_LIGHTSLEEP BIT(1)
#define MEM_AUX_DEEPSLEEP BIT(2)
/**
* @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
* Set the flag to inform
@@ -40,6 +45,11 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass)
LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
}
FORCE_INLINE_ATTR bool lp_sys_ll_get_pau_aon_bypass(void)
{
return LP_SYS.backup_dma_cfg1.aon_bypass;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_tout_thres_aon = tout;
@@ -60,6 +70,17 @@ FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr)
LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
FORCE_INLINE_ATTR void lp_sys_ll_set_hp_mem_lowpower_mode(uint32_t mode)
{
LP_SYS.hp_mem_aux_ctrl.hp_mem_lowpower_mode = mode;
}
FORCE_INLINE_ATTR void lp_sys_ll_set_lp_mem_lowpower_mode(uint32_t mode)
{
LP_SYS.lp_mem_aux_ctrl.lp_mem_lowpower_mode = mode;
}
#endif
#ifdef __cplusplus
}
#endif