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fix(esp_rom): implement cache writeback related apis in iram

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avoid critical issues caused by manual cache writeback and conflicting
writes. The issue exist on chips after esp32p4
This commit is contained in:
wanglei
2026-05-22 10:19:35 +08:00
parent 128defc06a
commit 85f79ecb07
19 changed files with 273 additions and 25 deletions
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components/esp_rom/esp32c61/Kconfig.soc_caps.in
+4
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@@ -118,3 +118,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
config ESP_ROM_DELAY_US_PATCH
bool
default y
config ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP
bool
default y
components/esp_rom/esp32c61/esp_rom_caps.h
+1
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@@ -35,3 +35,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation
#define ESP_ROM_CACHE_WRITEBACK_NEEDS_SYNC_TWICE_NO_MAP (1) // ROM cache writeback related needs patch to avoid sync loss, no map parameter
components/esp_rom/esp32c61/include/esp32c61/rom/cache.h
+2
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@@ -49,6 +49,8 @@ typedef enum {
CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
} cache_sync_t;
#define CACHE_MAP_FLASH_CACHE BIT(4)
typedef enum {
CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */
CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */
components/esp_rom/esp32c61/ld/esp32c61.rom.ld
+5 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -188,12 +188,12 @@ Cache_Sync_Items = 0x4000062c;
Cache_Op_Addr = 0x40000630;
Cache_Invalidate_Addr = 0x40000634;
Cache_Clean_Addr = 0x40000638;
Cache_WriteBack_Addr = 0x4000063c;
Cache_WriteBack_Invalidate_Addr = 0x40000640;
PROVIDE( Cache_WriteBack_Addr = 0x4000063c );
PROVIDE( Cache_WriteBack_Invalidate_Addr = 0x40000640 );
Cache_Invalidate_All = 0x40000644;
Cache_Clean_All = 0x40000648;
Cache_WriteBack_All = 0x4000064c;
Cache_WriteBack_Invalidate_All = 0x40000650;
PROVIDE( Cache_WriteBack_All = 0x4000064c );
PROVIDE( Cache_WriteBack_Invalidate_All = 0x40000650 );
Cache_Mask_All = 0x40000654;
Cache_UnMask_Dram0 = 0x40000658;
Cache_Suspend_Autoload = 0x4000065c;