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Merge branch 'fix/fix_esp32_int_wdt_workaround_break_sleep_process_v6.0' into 'release/v6.0'

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fix(esp_system): disable esp32 cache livelock int_wdt workaround in ipc_isr_stall (v6.0)

See merge request espressif/esp-idf!46741
This commit is contained in:
Jiang Jiang Jian
2026-03-21 14:11:21 +08:00
parent aca3ee3633 689e117be5
commit 85db04992a
9 changed files with 315 additions and 89 deletions
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components/esp_hw_support/port/esp32/chip_info.c
+2 -1
View File
@@ -6,6 +6,7 @@
#include <string.h>
#include "esp_chip_info.h"
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/chip_revision.h"
#include "soc/efuse_reg.h"
@@ -42,7 +43,7 @@ void esp_chip_info(esp_chip_info_t* out_info)
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
IRAM_ATTR inline bool soc_has_cache_lock_bug(void)
{
unsigned rev = efuse_hal_chip_revision();
return ESP_CHIP_REV_ABOVE(rev, 300);
components/esp_hw_support/sleep_modes.c
+22
View File
@@ -135,6 +135,10 @@
#include "hal/clk_gate_ll.h"
#endif
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#include "esp_private/eco3_livelock_workaround.h"
#endif
#if SOC_MSPI_HAS_INDEPENT_IOMUX
#include "hal/mspi_ll.h"
#endif
@@ -1175,6 +1179,11 @@ static esp_err_t FORCE_IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
esp_os_enter_critical(&spinlock_rtc_deep_sleep);
esp_ipc_isr_stall_other_cpu();
esp_ipc_isr_stall_pause();
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
// The other core will be stalled by high-priority interrupt and spins on variables in internal RAM,
// which naturally avoids cache livelock, so the 20ms livelock workaround timeout is not needed.
esp_int_wdt_livelock_workaround(false);
#endif
// record current RTC time
s_config.rtc_ticks_at_sleep_start = rtc_time_get();
@@ -1241,6 +1250,10 @@ static esp_err_t FORCE_IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
ESP_INFINITE_LOOP();
}
// Never returns here, except that the sleep is rejected.
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
// Configure WDT to use livelock workaround timeout after releasing other CPU
esp_int_wdt_livelock_workaround(true);
#endif
esp_ipc_isr_stall_resume();
esp_ipc_isr_release_other_cpu();
esp_os_exit_critical(&spinlock_rtc_deep_sleep);
@@ -1381,6 +1394,11 @@ esp_err_t esp_light_sleep_start(void)
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
sleep_smp_cpu_sleep_prepare();
#else
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
// The other core will be stalled by high-priority interrupt and spins on variables in internal RAM,
// which naturally avoids cache livelock, so the 20ms livelock workaround timeout is not needed.
esp_int_wdt_livelock_workaround(false);
#endif
esp_ipc_isr_stall_other_cpu();
#endif
esp_ipc_isr_stall_pause();
@@ -1569,6 +1587,10 @@ esp_err_t esp_light_sleep_start(void)
sleep_smp_cpu_wakeup_prepare();
#else
esp_ipc_isr_release_other_cpu();
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
// Configure WDT to use livelock workaround timeout after releasing other CPU
esp_int_wdt_livelock_workaround(true);
#endif
#endif
#endif