diff --git a/components/bootloader/subproject/main/ld/esp32c5/bootloader.sections.ld.in b/components/bootloader/subproject/main/ld/esp32c5/bootloader.sections.ld.in
index 4b2e639c228..330bf7c56ae 100644
--- a/components/bootloader/subproject/main/ld/esp32c5/bootloader.sections.ld.in
+++ b/components/bootloader/subproject/main/ld/esp32c5/bootloader.sections.ld.in
@@ -37,6 +37,7 @@
     *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*) \
     *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*) \
+    *libesp_security.a:esp_crypto_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*) \
     *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) \
diff --git a/components/bootloader/subproject/main/ld/esp32p4/bootloader.sections.ld.in b/components/bootloader/subproject/main/ld/esp32p4/bootloader.sections.ld.in
index f54803a1894..d4b3b2fff15 100644
--- a/components/bootloader/subproject/main/ld/esp32p4/bootloader.sections.ld.in
+++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.sections.ld.in
@@ -36,6 +36,7 @@
     *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*) \
     *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*) \
+    *libesp_security.a:esp_crypto_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*) \
     *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) \
@@ -74,6 +75,7 @@
     *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*) \
     *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*) \
     *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*) \
+    *libesp_security.a:esp_crypto_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*) \
     *libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) \
     *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) \
diff --git a/components/bootloader/subproject/main/ld/esp32s31/bootloader.sections.ld.in b/components/bootloader/subproject/main/ld/esp32s31/bootloader.sections.ld.in
index 4b2e639c228..330bf7c56ae 100644
--- a/components/bootloader/subproject/main/ld/esp32s31/bootloader.sections.ld.in
+++ b/components/bootloader/subproject/main/ld/esp32s31/bootloader.sections.ld.in
@@ -37,6 +37,7 @@
     *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*) \
     *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*) \
+    *libesp_security.a:esp_crypto_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*) \
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*) \
     *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*) \
diff --git a/components/esp_hal_clock/esp32p4/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32p4/include/hal/clk_gate_ll.h
index f2e17f105d4..f4191b593e5 100644
--- a/components/esp_hal_clock/esp32p4/include/hal/clk_gate_ll.h
+++ b/components/esp_hal_clock/esp32p4/include/hal/clk_gate_ll.h
@@ -245,9 +245,9 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
         REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN |
                     HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN);
         REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL20_REG, HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN |
-                    HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN);
+                    HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN);
         REG_CLR_BIT(HP_SYS_CLKRST_PERI_CLK_CTRL21_REG, HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN |
-                    HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN);
+                    HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN | HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN);
 
         REG_CLR_BIT(DSI_BRG_HOST_CTRL_REG, DSI_BRG_DSI_CFG_REF_CLK_EN);
         REG_CLR_BIT(SDHOST_CLK_EDGE_SEL_REG, SDHOST_CCLK_EN);
diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h
index 1352205bab1..9c0c219e399 100644
--- a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h
+++ b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h
@@ -12,9 +12,20 @@
 #include "soc/soc.h"
 #include "soc/reset_reasons.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/hp_alive_sys_struct.h"
+#include "soc/bus_monitor_struct.h"
+#include "soc/cnnt_sys_struct.h"
 #include "soc/lp_clkrst_struct.h"
 #include "soc/lp_clkrst_reg.h"
-#include "soc/hp_sys_clkrst_struct.h"
+#include "soc/lp_peri_clkrst_struct.h"
+#include "soc/lp_gpio_struct.h"
+#include "soc/usb_serial_jtag_struct.h"
+#include "soc/tee_struct.h"
+#include "soc/lp_tee_struct.h"
+#include "soc/hp_apm_struct.h"
+#include "soc/hp_mem_apm_struct.h"
+#include "soc/cpu_apm_struct.h"
+#include "soc/lp_apm_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -58,6 +69,171 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_25m_clk_en(bool enable)
 {
     HP_SYS_CLKRST.ref_25m_ctrl0.reg_ref_25m_clk_en = enable;
 }
+
+typedef struct {
+    bool disable_uart0_clk;           ///< Gate UART0 when it is not the console UART
+    bool disable_uart1_clk;           ///< Gate UART1 when it is not the console UART
+    bool disable_uart2_clk;           ///< Gate UART2 when it is not the console UART
+    bool disable_uart3_clk;           ///< Gate UART3 when it is not the console UART
+    bool disable_mspi_flash_clk;    ///< Gate MSPI flash clocks (e.g. PURE_RAM_APP)
+    bool keep_psram_hp_clk;         ///< Keep PSRAM MSPI root clocks when CONFIG_SPIRAM
+    bool disable_assist_clk;        ///< Gate bus monitor (assist) clocks when PC record unused
+    bool disable_crypto_periph_clk; ///< Gate crypto accelerators when TEE does not own them
+    bool disable_usb_serial_jtag;   ///< Gate USB Serial/JTAG when disabled in menuconfig
+} periph_ll_clk_gate_config_t;
+
+/**
+ * @brief Turn off unused peripheral root clocks after reset (HP_SYS_CLKRST + LP cleanup).
+ *
+ * Skips HP peripheral gating on CPU-local reset reasons so debug / SW reset keep clocks aligned
+ * with retained peripheral state. Does not touch CPU/cache/ICM/intrmtx/iomux skeleton clocks.
+ */
+static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason, const periph_ll_clk_gate_config_t *config)
+{
+    const bool skip_hp_periph_gate = (rst_reason == RESET_REASON_CPU_MWDT) ||
+                                     (rst_reason == RESET_REASON_CPU_SW) ||
+                                     (rst_reason == RESET_REASON_CPU_RWDT) ||
+                                     (rst_reason == RESET_REASON_CPU_JTAG) ||
+                                     (rst_reason == RESET_REASON_CPU_LOCKUP);
+
+    if (!skip_hp_periph_gate) {
+        // UART0~3
+        if (config->disable_uart0_clk) {
+            HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_sys_clk_en = 0;
+            HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_apb_clk_en = 0;
+            HP_SYS_CLKRST.uart0_ctrl0.reg_uart0_clk_en = 0;
+        }
+        if (config->disable_uart1_clk) {
+            HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_sys_clk_en = 0;
+            HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_apb_clk_en = 0;
+            HP_SYS_CLKRST.uart1_ctrl0.reg_uart1_clk_en = 0;
+        }
+        if (config->disable_uart2_clk) {
+            HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_sys_clk_en = 0;
+            HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_apb_clk_en = 0;
+            HP_SYS_CLKRST.uart2_ctrl0.reg_uart2_clk_en = 0;
+        }
+        if (config->disable_uart3_clk) {
+            HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_sys_clk_en = 0;
+            HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_apb_clk_en = 0;
+            HP_SYS_CLKRST.uart3_ctrl0.reg_uart3_clk_en = 0;
+        }
+        HP_ALIVE_SYS.hp_pad_uart0_ctrl.hp_pad_uart0_slp_clk_en = 0;
+        HP_ALIVE_SYS.hp_pad_uart1_ctrl.hp_pad_uart1_slp_clk_en = 0;
+        HP_ALIVE_SYS.hp_pad_uart2_ctrl.hp_pad_uart2_slp_clk_en = 0;
+        HP_ALIVE_SYS.hp_pad_uart3_ctrl.hp_pad_uart3_slp_clk_en = 0;
+        // ETM
+        HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_en = 0;
+        // Trace & Bus Monitor (0)
+        HP_SYS_CLKRST.trace_ctrl0.reg_trace_cpu_clk_en = 0;
+        HP_SYS_CLKRST.trace_ctrl0.reg_trace_sys_clk_en = 0;
+        // Assist Debug
+        if (config->disable_assist_clk) {
+            BUS_MONITOR.clock_gate.clk_en = 0;
+        }
+        // AXI DMA / AHB DMA / REGDMA / GDMA
+        HP_SYS_CLKRST.axi_pdma_ctrl0.reg_axi_pdma_sys_clk_en    = 0;
+        HP_SYS_CLKRST.ahb_pdma_ctrl0.reg_ahb_pdma_sys_clk_en    = 0;
+        HP_SYS_CLKRST.regdma_ctrl0.reg_regdma_sys_clk_en        = 0;
+        HP_ALIVE_SYS.hp_pad_parlio_ctrl.hp_pad_parlio_tx_clk_en = 0;
+        HP_ALIVE_SYS.hp_pad_parlio_ctrl.hp_pad_parlio_rx_clk_en = 0;
+        // I2S0-1
+        HP_ALIVE_SYS.hp_pad_i2s0_ctrl.hp_pad_i2s0_mclk_en = 0;
+        HP_ALIVE_SYS.hp_pad_i2s1_ctrl.hp_pad_i2s1_mclk_en = 0;
+        // TIMG0-1
+        HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_apb_clk_en = 0;
+        HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_t0_clk_en = 0;
+        HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_t1_clk_en = 0;
+        HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_wdt_clk_en = 0;
+        HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_apb_clk_en = 0;
+        HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t0_clk_en = 0;
+        HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_t1_clk_en = 0;
+        HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_wdt_clk_en = 0;
+        // LCDCAM
+        /*
+         * Default lcdcam_lcdcam_ctrl0:
+         *   reg_lcdcam_clk_src_sel: 1 (BBPLL 120 MHz path, shared by LCD and CAM)
+         *   reg_lcdcam_clk_div_num: 1 (divide by 2 → 60 MHz)
+         */
+        HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1;
+        HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_div_num = 1;
+        // ASRC
+        HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_sys_clk_en = 0;
+        // Flash
+        if (config->disable_mspi_flash_clk) {
+            HP_SYS_CLKRST.flash_ctrl0.reg_flash_sys_clk_en = 0;
+            HP_SYS_CLKRST.flash_ctrl0.reg_flash_pll_clk_en = 0;
+            HP_SYS_CLKRST.flash_ctrl0.reg_flash_core_clk_en = 0;
+        }
+        // PSRAM
+        if (!config->keep_psram_hp_clk) {
+            HP_SYS_CLKRST.psram_ctrl0.reg_psram_sys_clk_en = 0;
+            HP_SYS_CLKRST.psram_ctrl0.reg_psram_pll_clk_en = 0;
+            HP_SYS_CLKRST.psram_ctrl0.reg_psram_core_clk_en = 0;
+        }
+        // MSPI
+        if (config->disable_mspi_flash_clk && !config->keep_psram_hp_clk) {
+            HP_SYS_CLKRST.mspi_pad_ctrl0.reg_mspi_pad_ctrl_apb_clk_en = 0;
+        }
+        // GPSPI
+        HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_sys_clk_en = 0;
+        HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_apb_clk_en = 0;
+        HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_hs_clk_en = 0;
+        HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_mst_clk_en = 0;
+        HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_sys_clk_en = 0;
+        HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_apb_clk_en = 0;
+        HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_hs_clk_en = 0;
+        HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_mst_clk_en = 0;
+        // HP I2C master
+        HP_SYS_CLKRST.hp_i2cmst_ctrl0.reg_hp_i2cmst_apb_clk_en = 0;
+        // Crypto + security monitors (TEE/APM)
+        if (config->disable_crypto_periph_clk) {
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_aes_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sha_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_rsa_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ds_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ecc_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_hmac_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_ecdsa_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_rma_clk_en = 0;
+            HP_SYS_CLKRST.key_manager_ctrl0.reg_key_manager_sys_clk_en = 0;
+            HP_SYS_CLKRST.key_manager_ctrl0.reg_crypto_km_clk_en = 0;
+            TEE.clock_gate.clk_en = 0;
+            LP_TEE.clock_gate.clk_en = 0;
+            HP_APM.clock_gate.clk_en = 0;
+            HP_MEM_APM.clock_gate.clk_en = 0;
+            CPU_APM.clock_gate.clk_en = 0;
+        }
+        // UTMI
+        CNNT_SYS_REG.sys_usb_otg20_ctrl.sys_usb_otg20_utmifs_clk_en = 0;
+        // USB-Serial-JTAG
+        if (config->disable_usb_serial_jtag) {
+            USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+            HP_SYS_CLKRST.usb_device_ctrl0.reg_usb_device_apb_clk_en = 0;
+            USB_SERIAL_JTAG.mem_conf.usb_mem_pd = 1;
+            USB_SERIAL_JTAG.mem_conf.usb_mem_clk_en = 0;
+            CNNT_SYS_REG.sys_hp_usb_device_ctrl.sys_usb_device_48m_clk_en = 0;
+        }
+    }
+
+    if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_BROWN_OUT) ||
+            (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) ||
+            (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC)) {
+        LP_GPIO.clock_gate.clk_en = 0;
+        while (LP_GPIO.clock_gate.clk_en != 0) {
+            ;
+        }
+        LP_PERI_CLKRST.i2cmst_ctrl.lp_i2cmst_clk_en      = 0;
+        LP_PERI_CLKRST.touch_ctrl.lp_touch_clk_en        = 0;
+        LP_PERI_CLKRST.rng_ctrl.lp_rng_clk_en            = 0;
+        LP_PERI_CLKRST.dm_ctrl.lp_dm_clk_en              = 0;
+        if (config->disable_crypto_periph_clk) {
+            LP_APM.clock_gate.clk_en = 0;
+        }
+    }
+}
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
 #define clk_gate_ll_ref_25m_clk_en(...) do { \
@@ -125,29 +301,6 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable)
         _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__); \
     } while(0)
 
-/**
- * @brief Set the default clock gate configuration
- */
-static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason)
-{
-    if ((rst_reason == RESET_REASON_CHIP_POWER_ON)   || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN) ||
-            (rst_reason == RESET_REASON_SYS_BROWN_OUT)   || (rst_reason == RESET_REASON_SYS_RWDT) ||
-            (rst_reason == RESET_REASON_SYS_SUPER_WDT)   || (rst_reason == RESET_REASON_CORE_SW) ||
-            (rst_reason == RESET_REASON_CORE_MWDT0)      || (rst_reason == RESET_REASON_CORE_MWDT1) ||
-            (rst_reason == RESET_REASON_CORE_RWDT)       || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) ||
-            (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) ||
-            (rst_reason == RESET_REASON_CORE_USB_UART)
-       ) {
-        /*
-         * Default lcdcam_lcdcam_ctrl0:
-         *   reg_lcdcam_clk_src_sel: 1 (BBPLL 120 MHz path, shared by LCD and CAM)
-         *   reg_lcdcam_clk_div_num: 1 (divide by 2 → 60 MHz)
-         */
-        HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_src_sel = 1;
-        HP_SYS_CLKRST.lcdcam_lcdcam_ctrl0.reg_lcdcam_clk_div_num = 1;
-    }
-}
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hal_wdt/esp32p4/include/hal/mwdt_ll.h b/components/esp_hal_wdt/esp32p4/include/hal/mwdt_ll.h
index 0952cebed97..4fad9ba94f5 100644
--- a/components/esp_hal_wdt/esp32p4/include/hal/mwdt_ll.h
+++ b/components/esp_hal_wdt/esp32p4/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -289,16 +289,22 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc
  * @param en true to enable, false to disable
  */
 __attribute__((always_inline))
-static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
+static inline void _mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
 {
-    /* The clock always defaults to enabled on P4.
-       If we update to be able to enable/disable the clock then this function
-       needs to be protected with PERIPH_RCC_ATOMIC as it touches shared registers.
-     */
-    (void)hw;
-    (void)en;
+    if (hw == &TIMERG0) {
+        HP_SYS_CLKRST.peri_clk_ctrl20.reg_timergrp0_wdt_clk_en = en;
+    } else {
+        HP_SYS_CLKRST.peri_clk_ctrl21.reg_timergrp1_wdt_clk_en = en;
+    }
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mwdt_ll_enable_clock(...) do { \
+        (void)__DECLARE_RCC_ATOMIC_ENV; \
+        _mwdt_ll_enable_clock(__VA_ARGS__); \
+    } while(0)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hal_wdt/esp32p4/rom.wdt.ld b/components/esp_hal_wdt/esp32p4/rom.wdt.ld
index ed3bfd3d81e..11277bed6b0 100644
--- a/components/esp_hal_wdt/esp32p4/rom.wdt.ld
+++ b/components/esp_hal_wdt/esp32p4/rom.wdt.ld
@@ -18,8 +18,8 @@
  ***************************************/
 
 /* Functions */
-wdt_hal_init = 0x4fc001fc;
-wdt_hal_deinit = 0x4fc00200;
+rom_wdt_hal_init = 0x4fc001fc;
+rom_wdt_hal_deinit = 0x4fc00200;
 rom_wdt_hal_config_stage = 0x4fc00204;
 wdt_hal_write_protect_disable = 0x4fc00208;
 wdt_hal_write_protect_enable = 0x4fc0020c;
diff --git a/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h b/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h
index 7d11279f61e..87f8413add7 100644
--- a/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h
+++ b/components/esp_hal_wdt/esp32s31/include/hal/mwdt_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -289,16 +289,22 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc
 * @param en true to enable, false to disable
 */
 __attribute__((always_inline))
-static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
+static inline void _mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
 {
-    /* The clock always defaults to enabled on P4.
-    If we update to be able to enable/disable the clock then this function
-    needs to be protected with PERIPH_RCC_ATOMIC as it touches shared registers.
-    */
-    (void)hw;
-    (void)en;
+    if (hw == &TIMERG0) {
+        HP_SYS_CLKRST.timergrp0_ctrl0.reg_timergrp0_wdt_clk_en = en;
+    } else {
+        HP_SYS_CLKRST.timergrp1_ctrl0.reg_timergrp1_wdt_clk_en = en;
+    }
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mwdt_ll_enable_clock(...) do { \
+        (void)__DECLARE_RCC_ATOMIC_ENV; \
+        _mwdt_ll_enable_clock(__VA_ARGS__); \
+    } while(0)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hal_wdt/rom_patch.c b/components/esp_hal_wdt/rom_patch.c
index 4bbe42b512d..a55081f9fcf 100644
--- a/components/esp_hal_wdt/rom_patch.c
+++ b/components/esp_hal_wdt/rom_patch.c
@@ -21,6 +21,8 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
     if (hal->inst != WDT_RWDT) {
         mwdt_ll_write_protect_disable(hal->mwdt_dev);
         mwdt_ll_set_clock_source(hal->mwdt_dev, MWDT_CLK_SRC_DEFAULT);
+        // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+        int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
         mwdt_ll_enable_clock(hal->mwdt_dev, true);
         mwdt_ll_write_protect_enable(hal->mwdt_dev);
     }
@@ -31,6 +33,8 @@ void wdt_hal_deinit(wdt_hal_context_t *hal)
     // ROM version omits mwdt_ll_enable_clock(false) — delegate to ROM then fix up
     if (hal->inst != WDT_RWDT) {
         mwdt_ll_write_protect_disable(hal->mwdt_dev);
+        // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+        int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
         mwdt_ll_enable_clock(hal->mwdt_dev, false);
         mwdt_ll_write_protect_enable(hal->mwdt_dev);
     }
diff --git a/components/esp_hal_wdt/wdt_hal_iram.c b/components/esp_hal_wdt/wdt_hal_iram.c
index d256a0abcfa..ab16d4cc02f 100644
--- a/components/esp_hal_wdt/wdt_hal_iram.c
+++ b/components/esp_hal_wdt/wdt_hal_iram.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -79,6 +79,8 @@ void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescale
         mwdt_ll_set_cpu_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
         mwdt_ll_set_sys_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
         mwdt_ll_set_clock_source(hal->mwdt_dev, MWDT_CLK_SRC_DEFAULT);
+        // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+        int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
         mwdt_ll_enable_clock(hal->mwdt_dev, true);
         //Set tick period
         mwdt_ll_set_prescaler(hal->mwdt_dev, prescaler);
@@ -107,6 +109,8 @@ void wdt_hal_deinit(wdt_hal_context_t *hal)
         mwdt_ll_disable(hal->mwdt_dev);
         mwdt_ll_clear_intr_status(hal->mwdt_dev);
         mwdt_ll_set_intr_enable(hal->mwdt_dev, false);
+        // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+        int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
         mwdt_ll_enable_clock(hal->mwdt_dev, false);
         //Lock WDT
         mwdt_ll_write_protect_enable(hal->mwdt_dev);
diff --git a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
index 48b4555cd97..a8e793b9089 100644
--- a/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
@@ -273,13 +273,13 @@ typedef struct {
 #define PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags) {                               \
     .hp_sys = {                                                                     \
         .dig_power = {                                                              \
-            .vdd_spi_pd_en      = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0,   \
-            .pd_hp_alive_pd_en  = 0,                                                \
-            .pd_modem_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0,     \
-            .pd_hp_cnnt_pd_en   = ((sleep_flags) & PMU_SLEEP_PD_CNNT) ? 1 : 0,      \
-            .pd_hp_cpu_pd_en    = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0,       \
-            .pd_modem_pwr_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MEM) ? 1 : 0,     \
-            .pd_top_pd_en       = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0,       \
+            .vdd_spi_pd_en      = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO)   ? 1 : 0, \
+            .pd_hp_alive_pd_en  = ((sleep_flags) & PMU_SLEEP_PD_MEM)       ? 1 : 0, \
+            .pd_modem_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM)     ? 1 : 0, \
+            .pd_hp_cnnt_pd_en   = ((sleep_flags) & PMU_SLEEP_PD_CNNT)      ? 1 : 0, \
+            .pd_hp_cpu_pd_en    = ((sleep_flags) & PMU_SLEEP_PD_CPU)       ? 1 : 0, \
+            .pd_modem_pwr_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MEM)       ? 1 : 0, \
+            .pd_top_pd_en       = ((sleep_flags) & PMU_SLEEP_PD_TOP)       ? 1 : 0, \
             .pd_hp_mem_pd_en    = 0,                                                \
             .mem_dslp           = 0,                                                \
         },                                                                          \
diff --git a/components/esp_security/CMakeLists.txt b/components/esp_security/CMakeLists.txt
index fe08fb3e07a..c3568afce4e 100644
--- a/components/esp_security/CMakeLists.txt
+++ b/components/esp_security/CMakeLists.txt
@@ -8,11 +8,10 @@ endif()
 set(srcs "")
 set(requires esp_hal_security)
 set(priv_requires esp_hw_support hal efuse)
-set(priv_includes "")
+set(priv_includes "src/${IDF_TARGET}")
 
 if(NOT non_os_build)
     list(APPEND srcs "src/init.c")
-    list(APPEND priv_includes "src/${IDF_TARGET}")
 
     if(CONFIG_SOC_HMAC_SUPPORTED)
         list(APPEND srcs "src/esp_hmac.c")
@@ -30,11 +29,12 @@ if(NOT non_os_build)
         list(APPEND srcs "src/esp_dpa_protection.c")
     endif()
 
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
+                    "src/${target}/esp_crypto_clk.c")
     list(APPEND priv_requires esp_system esp_timer)
 elseif(esp_tee_build)
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
-    list(APPEND includes "src/${IDF_TARGET}")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
+                    "src/${target}/esp_crypto_clk.c")
 
     if(CONFIG_SOC_HMAC_SUPPORTED)
         list(APPEND srcs "src/esp_hmac.c")
@@ -44,7 +44,8 @@ elseif(esp_tee_build)
         list(APPEND srcs "src/esp_ds.c")
     endif()
 else()  # BOOTLOADER_BUILD
-    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
+    list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c"
+                    "src/${target}/esp_crypto_clk.c")
 
     if(CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY)
         list(APPEND srcs "src/esp_key_mgr.c")
diff --git a/components/esp_security/src/esp32/esp_crypto_clk.c b/components/esp_security/src/esp32/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32/esp_crypto_clk.h b/components/esp_security/src/esp32/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32c2/esp_crypto_clk.c b/components/esp_security/src/esp32c2/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32c2/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32c2/esp_crypto_clk.h b/components/esp_security/src/esp32c2/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32c2/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32c2/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32c3/esp_crypto_clk.c b/components/esp_security/src/esp32c3/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32c3/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32c3/esp_crypto_clk.h b/components/esp_security/src/esp32c3/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32c3/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32c3/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32c5/esp_crypto_clk.c b/components/esp_security/src/esp32c5/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32c5/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32c5/esp_crypto_clk.h b/components/esp_security/src/esp32c5/esp_crypto_clk.h
index b983ad446ef..caca106b28f 100644
--- a/components/esp_security/src/esp32c5/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32c5/esp_crypto_clk.h
@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 480M SPLL clock
diff --git a/components/esp_security/src/esp32c6/esp_crypto_clk.c b/components/esp_security/src/esp32c6/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32c6/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32c6/esp_crypto_clk.h b/components/esp_security/src/esp32c6/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32c6/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32c6/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32c61/esp_crypto_clk.c b/components/esp_security/src/esp32c61/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32c61/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32c61/esp_crypto_clk.h b/components/esp_security/src/esp32c61/esp_crypto_clk.h
index b983ad446ef..caca106b28f 100644
--- a/components/esp_security/src/esp32c61/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32c61/esp_crypto_clk.h
@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 480M SPLL clock
diff --git a/components/esp_security/src/esp32h2/esp_crypto_clk.c b/components/esp_security/src/esp32h2/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32h2/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32h2/esp_crypto_clk.h b/components/esp_security/src/esp32h2/esp_crypto_clk.h
index f56da300581..74f36a220b4 100644
--- a/components/esp_security/src/esp32h2/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32h2/esp_crypto_clk.h
@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock
diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.c b/components/esp_security/src/esp32h21/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32h21/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.h b/components/esp_security/src/esp32h21/esp_crypto_clk.h
index 33184965077..79c490ff53b 100644
--- a/components/esp_security/src/esp32h21/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32h21/esp_crypto_clk.h
@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock
diff --git a/components/esp_security/src/esp32h4/esp_crypto_clk.c b/components/esp_security/src/esp32h4/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32h4/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32h4/esp_crypto_clk.h b/components/esp_security/src/esp32h4/esp_crypto_clk.h
index 9c17dc8ea29..26f66ddacdd 100644
--- a/components/esp_security/src/esp32h4/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32h4/esp_crypto_clk.h
@@ -9,6 +9,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 96M PLL clock
diff --git a/components/esp_security/src/esp32p4/esp_crypto_clk.c b/components/esp_security/src/esp32p4/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32p4/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32p4/esp_crypto_clk.h b/components/esp_security/src/esp32p4/esp_crypto_clk.h
index 24cb45163a4..694dfa496cd 100644
--- a/components/esp_security/src/esp32p4/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32p4/esp_crypto_clk.h
@@ -8,6 +8,10 @@
 #include "esp_private/esp_clk_tree_common.h"
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 240M PLL clock
diff --git a/components/esp_security/src/esp32s2/esp_crypto_clk.c b/components/esp_security/src/esp32s2/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32s2/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32s2/esp_crypto_clk.h b/components/esp_security/src/esp32s2/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32s2/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32s2/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32s3/esp_crypto_clk.c b/components/esp_security/src/esp32s3/esp_crypto_clk.c
new file mode 100644
index 00000000000..8233631cfdf
--- /dev/null
+++ b/components/esp_security/src/esp32s3/esp_crypto_clk.c
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "esp_crypto_clk.h"
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+    (void)enable;
+}
diff --git a/components/esp_security/src/esp32s3/esp_crypto_clk.h b/components/esp_security/src/esp32s3/esp_crypto_clk.h
index 8fe1cce105e..1a79f850c77 100644
--- a/components/esp_security/src/esp32s3/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32s3/esp_crypto_clk.h
@@ -6,5 +6,9 @@
 
 #pragma once
 
+#include <stdbool.h>
+
+void esp_crypto_common_clk_enable(bool enable);
+
 /* nothing to do */
 static inline void esp_crypto_clk_init(void) {}
diff --git a/components/esp_security/src/esp32s31/esp_crypto_clk.c b/components/esp_security/src/esp32s31/esp_crypto_clk.c
new file mode 100644
index 00000000000..172f291e2ae
--- /dev/null
+++ b/components/esp_security/src/esp32s31/esp_crypto_clk.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_crypto_clk.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/hp_sys_clkrst_struct.h"
+#if !NON_OS_BUILD
+#include "esp_private/critical_section.h"
+#endif
+
+#if !NON_OS_BUILD
+DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
+#endif
+static int s_crypto_common_clk_ref_cnt;
+
+void esp_crypto_common_clk_enable(bool enable)
+{
+#if !NON_OS_BUILD
+    esp_os_enter_critical_safe(&s_crypto_common_clk_mux);
+#endif
+    if (enable) {
+        if (s_crypto_common_clk_ref_cnt++ == 0) {
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 1;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 1;
+        }
+    } else {
+        if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) {
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0;
+            HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0;
+        }
+    }
+#if !NON_OS_BUILD
+    esp_os_exit_critical_safe(&s_crypto_common_clk_mux);
+#endif
+}
diff --git a/components/esp_security/src/esp32s31/esp_crypto_clk.h b/components/esp_security/src/esp32s31/esp_crypto_clk.h
index f18deb1cb0a..094e8c7f6da 100644
--- a/components/esp_security/src/esp32s31/esp_crypto_clk.h
+++ b/components/esp_security/src/esp32s31/esp_crypto_clk.h
@@ -1,15 +1,20 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "soc/soc.h"
-#include "soc/hp_sys_clkrst_reg.h"
 
 #pragma once
 
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/hp_sys_clkrst_reg.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
 static inline void esp_crypto_clk_init(void)
 {
     // Set crypto clock (`clk_sec`) to use 240M PLL clock
     REG_SET_FIELD(HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2);
 }
+
+void esp_crypto_common_clk_enable(bool enable);
diff --git a/components/esp_security/src/esp_crypto_periph_clk.c b/components/esp_security/src/esp_crypto_periph_clk.c
index f5fa2dc2e79..0a84569af7b 100644
--- a/components/esp_security/src/esp_crypto_periph_clk.c
+++ b/components/esp_security/src/esp_crypto_periph_clk.c
@@ -8,6 +8,7 @@
 #include "esp_private/esp_crypto_lock_internal.h"
 #include "sdkconfig.h"
 #include "esp_crypto_periph_clk.h"
+#include "esp_crypto_clk.h"
 
 #if SOC_AES_SUPPORTED
 #include "hal/aes_ll.h"
@@ -48,6 +49,7 @@ int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
 void esp_crypto_aes_enable_periph_clk(bool enable)
 {
     AES_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         aes_ll_enable_bus_clock(enable);
         if (enable) {
             aes_ll_reset_register();
@@ -66,6 +68,7 @@ void esp_crypto_aes_enable_periph_clk(bool enable)
 void esp_crypto_sha_enable_periph_clk(bool enable)
 {
     SHA_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         sha_ll_enable_bus_clock(enable);
         if (enable) {
             sha_ll_reset_register();
@@ -84,6 +87,7 @@ void esp_crypto_sha_enable_periph_clk(bool enable)
 void esp_crypto_mpi_enable_periph_clk(bool enable)
 {
     MPI_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         mpi_ll_enable_bus_clock(enable);
         if (enable) {
             mpi_ll_power_up();
@@ -99,6 +103,7 @@ void esp_crypto_mpi_enable_periph_clk(bool enable)
 void esp_crypto_ecc_enable_periph_clk(bool enable)
 {
     ECC_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ecc_ll_enable_bus_clock(enable);
         if (enable) {
             ecc_ll_power_up();
@@ -114,6 +119,7 @@ void esp_crypto_ecc_enable_periph_clk(bool enable)
 void esp_crypto_hmac_enable_periph_clk(bool enable)
 {
     HMAC_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         hmac_ll_enable_bus_clock(enable);
         if (enable) {
             hmac_ll_reset_register();
@@ -126,6 +132,7 @@ void esp_crypto_hmac_enable_periph_clk(bool enable)
 void esp_crypto_ds_enable_periph_clk(bool enable)
 {
     DS_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ds_ll_enable_bus_clock(enable);
         if (enable) {
             ds_ll_reset_register();
@@ -138,6 +145,7 @@ void esp_crypto_ds_enable_periph_clk(bool enable)
 void esp_crypto_ecdsa_enable_periph_clk(bool enable)
 {
     ECDSA_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         ecdsa_ll_enable_bus_clock(enable);
         if (enable) {
             ecdsa_ll_reset_register();
@@ -150,6 +158,7 @@ void esp_crypto_ecdsa_enable_periph_clk(bool enable)
 void esp_crypto_key_mgr_enable_periph_clk(bool enable)
 {
     KEY_MANAGER_RCC_ATOMIC() {
+        esp_crypto_common_clk_enable(enable);
         key_mgr_ll_power_up();
         key_mgr_ll_enable_bus_clock(enable);
         key_mgr_ll_enable_peripheral_clock(enable);
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 752e9eef304..f3abf008924 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -252,7 +252,7 @@ void ESP_SYSTEM_IRAM_ATTR call_start_cpu1(void)
     esp_cpu_intr_set_mtvt_addr(&_mtvt_table);
 #endif
 #if SOC_CPU_SUPPORT_WFE
-    rv_utils_disable_wfe_mode();
+    esp_cpu_disable_wfe_mode();
 #endif
     ets_set_appcpu_boot_addr(0);
 
diff --git a/components/esp_system/port/soc/esp32s31/clk.c b/components/esp_system/port/soc/esp32s31/clk.c
index dc14844cfa3..5655994b386 100644
--- a/components/esp_system/port/soc/esp32s31/clk.c
+++ b/components/esp_system/port/soc/esp32s31/clk.c
@@ -30,6 +30,7 @@
 #include "esp_private/esp_pmu.h"
 #include "esp_rom_serial_output.h"
 #include "esp_rom_sys.h"
+#include "hal/clk_gate_ll.h"
 
 /* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
  * Larger values increase startup delay. Smaller values may cause false positive
@@ -196,5 +197,36 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
 #endif
 
-    periph_ll_clk_gate_set_default(esp_rom_get_reset_reason(0));
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    periph_ll_clk_gate_config_t clk_gate_config = {0};
+
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
+    clk_gate_config.disable_uart0_clk = true;
+#endif
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
+    clk_gate_config.disable_uart1_clk = true;
+#endif
+#if CONFIG_ESP_CONSOLE_UART_NUM != 2
+    clk_gate_config.disable_uart2_clk = true;
+#endif
+#if CONFIG_ESP_CONSOLE_UART_NUM != 3
+    clk_gate_config.disable_uart3_clk = true;
+#endif
+#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
+    clk_gate_config.disable_mspi_flash_clk = true;
+#endif
+#if CONFIG_SPIRAM
+    clk_gate_config.keep_psram_hp_clk = true;
+#endif
+#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
+    clk_gate_config.disable_assist_clk = true;
+#endif
+#if !CONFIG_SECURE_ENABLE_TEE
+    clk_gate_config.disable_crypto_periph_clk = true;
+#endif
+#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
+    clk_gate_config.disable_usb_serial_jtag = true;
+#endif
+
+    periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
 }
diff --git a/components/freertos/port_systick.c b/components/freertos/port_systick.c
index af877bcb15c..179d74b8390 100644
--- a/components/freertos/port_systick.c
+++ b/components/freertos/port_systick.c
@@ -75,6 +75,7 @@ void vSystimerSetup(void)
         PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_SYSTIMER_MODULE, ref_count) {
             if (ref_count == 0) {
                 systimer_ll_enable_bus_clock(true);
+                systimer_ll_enable_sys_clock(true);
                 systimer_ll_reset_register();
             }
         }
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index 44d2f9a7492..19c2359ecd8 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -507,6 +507,10 @@ config SOC_CPU_HAS_FLEXIBLE_INTC
     bool
     default y
 
+config SOC_CPU_SUPPORT_WFE
+    bool
+    default y
+
 config SOC_INT_CLIC_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index f7f25426e87..426ede839da 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -173,6 +173,7 @@
 #define SOC_CPU_CORES_NUM               (2U)
 #define SOC_CPU_INTR_NUM                32
 #define SOC_CPU_HAS_FLEXIBLE_INTC       1
+#define SOC_CPU_SUPPORT_WFE             1
 #define SOC_INT_CLIC_SUPPORTED          1
 #define SOC_INT_HW_NESTED_SUPPORTED     1       // Support for hardware interrupts nesting
 #define SOC_BRANCH_PREDICTOR_SUPPORTED  1
diff --git a/components/soc/esp32s31/ld/esp32s31.peripherals.ld b/components/soc/esp32s31/ld/esp32s31.peripherals.ld
index 10f103077d7..1b763c48f27 100644
--- a/components/soc/esp32s31/ld/esp32s31.peripherals.ld
+++ b/components/soc/esp32s31/ld/esp32s31.peripherals.ld
@@ -60,7 +60,7 @@ PROVIDE ( SPIMEM2             = 0x20502000 );
 PROVIDE ( SPIMEM3             = 0x20503000 );
 PROVIDE ( TEE                 = 0x20504000 );
 PROVIDE ( HP_APM              = 0x20504400 );
-PROVIDE ( HP_MEM              = 0x20504800 );
+PROVIDE ( HP_MEM_APM          = 0x20504800 );
 PROVIDE ( CPU_APM             = 0x20504C00 );
 PROVIDE ( HP_PERI0_PMS        = 0x20505000 );
 PROVIDE ( KEYMNG              = 0x20506000 );
diff --git a/components/soc/esp32s31/register/soc/cpu_apm_struct.h b/components/soc/esp32s31/register/soc/cpu_apm_struct.h
index f3d8b1fc48e..f0847b9646d 100644
--- a/components/soc/esp32s31/register/soc/cpu_apm_struct.h
+++ b/components/soc/esp32s31/register/soc/cpu_apm_struct.h
@@ -602,6 +602,7 @@ typedef struct {
     volatile cpu_apm_date_reg_t date;
 } cpu_apm_dev_t;
 
+extern cpu_apm_dev_t CPU_APM;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(cpu_apm_dev_t) == 0x400, "Invalid size of cpu_apm_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/hp_apm_struct.h b/components/soc/esp32s31/register/soc/hp_apm_struct.h
index ce2ba679d92..96c3c63bec9 100644
--- a/components/soc/esp32s31/register/soc/hp_apm_struct.h
+++ b/components/soc/esp32s31/register/soc/hp_apm_struct.h
@@ -886,6 +886,7 @@ typedef struct {
     volatile hp_apm_date_reg_t date;
 } hp_apm_dev_t;
 
+extern hp_apm_dev_t HP_APM;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(hp_apm_dev_t) == 0x400, "Invalid size of hp_apm_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
index b1cbe9e0fd7..016005336a8 100644
--- a/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
+++ b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
@@ -777,6 +777,7 @@ typedef struct {
     volatile hp_mem_apm_date_reg_t date;
 } hp_mem_apm_dev_t;
 
+extern hp_mem_apm_dev_t HP_MEM_APM;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(hp_mem_apm_dev_t) == 0x400, "Invalid size of hp_mem_apm_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/lp_apm_struct.h b/components/soc/esp32s31/register/soc/lp_apm_struct.h
index 785511fa8d8..aa7e0425357 100644
--- a/components/soc/esp32s31/register/soc/lp_apm_struct.h
+++ b/components/soc/esp32s31/register/soc/lp_apm_struct.h
@@ -588,6 +588,7 @@ typedef struct {
     volatile lp_apm_date_reg_t date;
 } lp_apm_dev_t;
 
+extern lp_apm_dev_t LP_APM;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_apm_dev_t) == 0x400, "Invalid size of lp_apm_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/lp_tee_struct.h b/components/soc/esp32s31/register/soc/lp_tee_struct.h
index 9411439f2c6..00ca6be3f5d 100644
--- a/components/soc/esp32s31/register/soc/lp_tee_struct.h
+++ b/components/soc/esp32s31/register/soc/lp_tee_struct.h
@@ -236,6 +236,7 @@ typedef struct {
     volatile lp_tee_date_reg_t date;
 } lp_tee_dev_t;
 
+extern lp_tee_dev_t LP_TEE;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_tee_dev_t) == 0x400, "Invalid size of lp_tee_dev_t structure");
diff --git a/components/soc/esp32s31/register/soc/tee_struct.h b/components/soc/esp32s31/register/soc/tee_struct.h
index 89c611da183..ab74d830c10 100644
--- a/components/soc/esp32s31/register/soc/tee_struct.h
+++ b/components/soc/esp32s31/register/soc/tee_struct.h
@@ -180,6 +180,7 @@ typedef struct {
     volatile tee_date_reg_t date;
 } tee_dev_t;
 
+extern tee_dev_t TEE;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(tee_dev_t) == 0x400, "Invalid size of tee_dev_t structure");
diff --git a/examples/lowpower/power_management/pytest_power_management.py b/examples/lowpower/power_management/pytest_power_management.py
index 485b724204c..8b11e69d9a3 100644
--- a/examples/lowpower/power_management/pytest_power_management.py
+++ b/examples/lowpower/power_management/pytest_power_management.py
@@ -61,8 +61,8 @@ def test_esp_pm_mode_stats_pd_top(dut: Dut) -> None:
 
 
 @pytest.mark.generic
-@pytest.mark.esp32c5_eco3
+@pytest.mark.esp32c5_rev1
 @pytest.mark.parametrize('config', ['pd_top'], indirect=True)
 @idf_parametrize('target', ['esp32c5'], indirect=['target'])
-def test_esp_pm_mode_stats_pd_top_esp32c5_eco3(dut: Dut) -> None:
+def test_esp_pm_mode_stats_pd_top_esp32c5_rev1(dut: Dut) -> None:
     _run_pm_example_test(dut)