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Merge branch 'refactor/remove_esp32h4_target_v5.1' into 'release/v5.1'

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esp32h4: remove esp32h4 target (v5.1)

See merge request espressif/esp-idf!23422
This commit is contained in:
Shu Chen
2023-04-27 09:37:51 +08:00
parent aedcec9be5 87328d594f
commit 856cfa4ae2
464 changed files with 281 additions and 117129 deletions
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2
docs/en/api-reference/peripherals/adc_calibration.rst
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@@ -119,7 +119,7 @@ For those users who use their custom ADC calibration schemes, you could either m
ESP_ERROR_CHECK(adc_cali_delete_scheme_curve_fitting(handle));
.. only:: esp32h4
.. only:: esp32h2
There is no supported calibration scheme yet.

2
docs/en/api-reference/peripherals/adc_continuous.rst
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@@ -1,7 +1,7 @@
Analog to Digital Converter (ADC) Continuous Mode Driver
========================================================
{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h4="one"}
{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"}
Introduction
------------

2
docs/en/api-reference/peripherals/adc_oneshot.rst
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@@ -1,7 +1,7 @@
Analog to Digital Converter (ADC) Oneshot Mode Driver
=====================================================
{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h4="one"}
{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one"}
Introduction
------------

4
docs/en/api-reference/peripherals/clk_tree.rst
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@@ -5,7 +5,7 @@ Clock Tree
{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5"}
{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32", esp32h2="32"}
{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h2="32"}
{IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"}
@@ -36,7 +36,7 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.
The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
.. only:: not SOC_CLK_RC_FAST_D256_SUPPORTED and SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.

4
docs/en/api-reference/peripherals/i2s.rst
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@@ -70,11 +70,11 @@ Clock Source
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_DEFAULT`: Default PLL clock.
.. only:: not esp32h4
.. only:: not esp32h2
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
.. only:: esp32h4
.. only:: esp32h2
- :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.

19
docs/en/api-reference/peripherals/ledc.rst
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@@ -189,25 +189,6 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- 32 MHz
- Dynamic Frequency Scaling compatible
.. only:: esp32h4
.. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
:widths: 15 15 30
:header-rows: 1
* - Clock name
- Clock freq
- Clock capabilities
* - APB_CLK
- 96 MHz
- /
* - RC_FAST_CLK
- ~8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
- 32 MHz
- Dynamic Frequency Scaling compatible
.. note::
.. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION