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change(soc): rename peripheral powerdowned sleep wakeable IO soc_caps

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rename SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
rename SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
rename SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP to SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
This commit is contained in:
wuzhenghui
2026-02-01 12:16:20 +08:00
committed by Jack
parent afa266ebd6
commit 85601ccb69
29 changed files with 98 additions and 92 deletions
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components/esp_driver_gpio/include/driver/gpio.h
+2 -2
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@@ -565,7 +565,7 @@ esp_err_t gpio_sleep_set_direction(gpio_num_t gpio_num, gpio_mode_t mode);
*/ */
esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull); esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ #define GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \
(((1ULL << (gpio_num)) & SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) != 0)) (((1ULL << (gpio_num)) & SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) != 0))
@@ -596,7 +596,7 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int
*/ */
esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num); esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num);
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
/** /**
* @brief Dump IO configuration information to console * @brief Dump IO configuration information to console
components/esp_driver_gpio/src/gpio.c
+2 -2
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@@ -1017,7 +1017,7 @@ esp_err_t gpio_sleep_sel_dis(gpio_num_t gpio_num)
return ESP_OK; return ESP_OK;
} }
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type) esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
{ {
if (!GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num)) { if (!GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num)) {
@@ -1057,7 +1057,7 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num)
portEXIT_CRITICAL(&gpio_context.gpio_spinlock); portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
return ESP_OK; return ESP_OK;
} }
#endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #endif // SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
esp_err_t gpio_get_io_config(gpio_num_t gpio_num, gpio_io_config_t *out_io_config) esp_err_t gpio_get_io_config(gpio_num_t gpio_num, gpio_io_config_t *out_io_config)
{ {
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
+2 -2
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@@ -235,7 +235,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
} }
#endif //SOC_RTCIO_HOLD_SUPPORTED #endif //SOC_RTCIO_HOLD_SUPPORTED
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0) #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
/* /*
* test interrupt functionality * test interrupt functionality
*/ */
@@ -275,7 +275,7 @@ TEST_CASE("RTCIO_interrupt_test", "[rtcio]")
rtcio_ll_intr_enable(test_io, GPIO_INTR_DISABLE); rtcio_ll_intr_enable(test_io, GPIO_INTR_DISABLE);
TEST_ESP_OK(rtc_gpio_deinit(test_io)); TEST_ESP_OK(rtc_gpio_deinit(test_io));
} }
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0) #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
#if SOC_DEEP_SLEEP_SUPPORTED #if SOC_DEEP_SLEEP_SUPPORTED
components/esp_driver_ledc/src/ledc.c
+1 -1
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@@ -1004,7 +1004,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
// To workaround DIG-399, all LP IOs are held when LP_PERIPH is powered off to ensure EXT wakeup functionality // To workaround DIG-399, all LP IOs are held when LP_PERIPH is powered off to ensure EXT wakeup functionality
// But holding LP IOs will cause LEDC signal cannot output on the pad during sleep // But holding LP IOs will cause LEDC signal cannot output on the pad during sleep
// Therefore, we will force LP periph xpd in such case // Therefore, we will force LP periph xpd in such case
if ((1ULL << gpio_num) & SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) { if (GPIO_IS_HP_PERIPH_PD_WAKEUP_VALID_IO(gpio_num)) {
esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
} }
#endif #endif
components/esp_hal_gpio/include/hal/gpio_hal.h
+2 -2
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@@ -497,7 +497,7 @@ void gpio_hal_matrix_out(gpio_hal_context_t *hal, uint32_t gpio_num, uint32_t si
*/ */
#define gpio_hal_sleep_output_enable(hal, gpio_num) gpio_ll_sleep_output_enable((hal)->dev, gpio_num) #define gpio_hal_sleep_output_enable(hal, gpio_num) gpio_ll_sleep_output_enable((hal)->dev, gpio_num)
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED
/** /**
* @brief Enable GPIO deep-sleep wake-up function. * @brief Enable GPIO deep-sleep wake-up function.
* *
@@ -524,7 +524,7 @@ void gpio_hal_matrix_out(gpio_hal_context_t *hal, uint32_t gpio_num, uint32_t si
* @return True if the pin is enabled to wake up from deep-sleep * @return True if the pin is enabled to wake up from deep-sleep
*/ */
#define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) gpio_ll_deepsleep_wakeup_is_enabled((hal)->dev, gpio_num) #define gpio_hal_deepsleep_wakeup_is_enabled(hal, gpio_num) gpio_ll_deepsleep_wakeup_is_enabled((hal)->dev, gpio_num)
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0)
#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER #if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
/** /**
components/esp_hal_gpio/include/hal/rtc_io_hal.h
+2 -2
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@@ -312,7 +312,7 @@ void rtcio_hal_isolate(int rtc_num);
#endif //SOC_RTCIO_PIN_COUNT > 0 #endif //SOC_RTCIO_PIN_COUNT > 0
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0) #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#define gpio_hal_deepsleep_wakeup_enable(hal, gpio_num, intr_type) rtcio_hal_wakeup_enable(rtc_io_num_map[gpio_num], intr_type) #define gpio_hal_deepsleep_wakeup_enable(hal, gpio_num, intr_type) rtcio_hal_wakeup_enable(rtc_io_num_map[gpio_num], intr_type)
#define gpio_hal_deepsleep_wakeup_disable(hal, gpio_num) rtcio_hal_wakeup_disable(rtc_io_num_map[gpio_num]) #define gpio_hal_deepsleep_wakeup_disable(hal, gpio_num) rtcio_hal_wakeup_disable(rtc_io_num_map[gpio_num])
@@ -341,7 +341,7 @@ void rtcio_hal_isolate(int rtc_num);
*/ */
#define rtcio_hal_clear_interrupt_status() rtcio_ll_clear_interrupt_status() #define rtcio_hal_clear_interrupt_status() rtcio_ll_clear_interrupt_status()
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0) #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT > 0)
#ifdef __cplusplus #ifdef __cplusplus
} }
components/esp_hal_pmu/include/hal/rtc_hal.h
+2 -1
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@@ -80,7 +80,8 @@ typedef struct rtc_cntl_sleep_retent {
#endif #endif
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP #endif // SOC_PM_SUPPORT_EXT1_WAKEUP
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && (SOC_RTCIO_PIN_COUNT == 0) && SOC_DEEP_SLEEP_SUPPORTED
#define rtc_hal_gpio_get_wakeup_status() rtc_cntl_ll_gpio_get_wakeup_status() #define rtc_hal_gpio_get_wakeup_status() rtc_cntl_ll_gpio_get_wakeup_status()
#define rtc_hal_gpio_clear_wakeup_status() rtc_cntl_ll_gpio_clear_wakeup_status() #define rtc_hal_gpio_clear_wakeup_status() rtc_cntl_ll_gpio_clear_wakeup_status()
#endif #endif
components/esp_hw_support/include/esp_sleep.h
+4 -4
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@@ -41,7 +41,7 @@ typedef enum {
#endif #endif
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
typedef enum { typedef enum {
ESP_GPIO_WAKEUP_GPIO_LOW = 0, ESP_GPIO_WAKEUP_GPIO_LOW = 0,
ESP_GPIO_WAKEUP_GPIO_HIGH = 1 ESP_GPIO_WAKEUP_GPIO_HIGH = 1
@@ -452,7 +452,7 @@ __attribute__((deprecated("please use 'esp_sleep_enable_ext1_wakeup_io' and 'esp
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN #endif // SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP #endif // SOC_PM_SUPPORT_EXT1_WAKEUP
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
/** /**
* @brief Enable wakeup using specific gpio pins * @brief Enable wakeup using specific gpio pins
* *
@@ -581,7 +581,7 @@ esp_err_t esp_sleep_disable_wifi_beacon_wakeup(void);
*/ */
uint64_t esp_sleep_get_ext1_wakeup_status(void); uint64_t esp_sleep_get_ext1_wakeup_status(void);
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
/** /**
* @brief Get the bit mask of GPIOs which caused wakeup (gpio) * @brief Get the bit mask of GPIOs which caused wakeup (gpio)
* *
@@ -590,7 +590,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void);
* @return bit mask, if GPIOn caused wakeup, BIT(n) will be set * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
*/ */
uint64_t esp_sleep_get_gpio_wakeup_status(void); uint64_t esp_sleep_get_gpio_wakeup_status(void);
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
/** /**
* @brief Configure power domain options for sleep mode * @brief Configure power domain options for sleep mode
components/esp_hw_support/sleep_gpio.c
+2 -2
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@@ -244,8 +244,8 @@ void esp_deep_sleep_wakeup_io_reset(void)
} }
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
uint32_t dl_io_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK; uint32_t dl_io_mask = SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK;
gpio_hal_context_t gpio_hal = { gpio_hal_context_t gpio_hal = {
.dev = GPIO_HAL_GET_HW(GPIO_PORT_0) .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
}; };
components/esp_hw_support/sleep_modes.c
+10 -10
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@@ -273,9 +273,9 @@ typedef struct {
uint32_t ext0_trigger_level : 1; uint32_t ext0_trigger_level : 1;
uint32_t ext0_rtc_gpio_num : 5; uint32_t ext0_rtc_gpio_num : 5;
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
uint32_t gpio_wakeup_mask : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT; // Only RTC_GPIO supports wakeup deepsleep uint32_t gpio_wakeup_mask : SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT;
uint32_t gpio_trigger_mode : SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT; uint32_t gpio_trigger_mode : SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT;
#endif #endif
uint32_t sleep_time_adjustment; uint32_t sleep_time_adjustment;
uint32_t ccount_ticks_record; uint32_t ccount_ticks_record;
@@ -364,7 +364,7 @@ static void touch_wakeup_prepare(void);
#if SOC_VBAT_SUPPORTED #if SOC_VBAT_SUPPORTED
static void vbat_under_volt_wakeup_prepare(void); static void vbat_under_volt_wakeup_prepare(void);
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
static void gpio_deep_sleep_wakeup_prepare(void); static void gpio_deep_sleep_wakeup_prepare(void);
#endif #endif
@@ -987,7 +987,7 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t cl
// for !(s_config.wakeup_triggers & RTC_EXT1_TRIG_EN), ext1 wakeup will be turned off in hardware in the real call to sleep // for !(s_config.wakeup_triggers & RTC_EXT1_TRIG_EN), ext1 wakeup will be turned off in hardware in the real call to sleep
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
if (deep_sleep && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) { if (deep_sleep && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
gpio_deep_sleep_wakeup_prepare(); gpio_deep_sleep_wakeup_prepare();
} }
@@ -1841,7 +1841,7 @@ bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
{ {
#if SOC_RTCIO_PIN_COUNT > 0 #if SOC_RTCIO_PIN_COUNT > 0
return RTC_GPIO_IS_VALID_GPIO(gpio_num); return RTC_GPIO_IS_VALID_GPIO(gpio_num);
#elif SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #elif SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num); return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
#else #else
return false; return false;
@@ -2069,7 +2069,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status(void)
#endif // SOC_PM_SUPPORT_EXT1_WAKEUP && SOC_RTCIO_PIN_COUNT > 0 #endif // SOC_PM_SUPPORT_EXT1_WAKEUP && SOC_RTCIO_PIN_COUNT > 0
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
uint64_t esp_sleep_get_gpio_wakeup_status(void) uint64_t esp_sleep_get_gpio_wakeup_status(void)
{ {
if (!(esp_sleep_get_wakeup_causes() & BIT(ESP_SLEEP_WAKEUP_GPIO))) { if (!(esp_sleep_get_wakeup_causes() & BIT(ESP_SLEEP_WAKEUP_GPIO))) {
@@ -2080,7 +2080,7 @@ uint64_t esp_sleep_get_gpio_wakeup_status(void)
static void gpio_deep_sleep_wakeup_prepare(void) static void gpio_deep_sleep_wakeup_prepare(void)
{ {
uint32_t valid_wake_io_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK; uint32_t valid_wake_io_mask = SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK;
for (gpio_num_t gpio_idx = __builtin_ctz(valid_wake_io_mask); valid_wake_io_mask >> gpio_idx; gpio_idx++) { for (gpio_num_t gpio_idx = __builtin_ctz(valid_wake_io_mask); valid_wake_io_mask >> gpio_idx; gpio_idx++) {
if ((s_config.gpio_wakeup_mask & BIT64(gpio_idx)) == 0) { if ((s_config.gpio_wakeup_mask & BIT64(gpio_idx)) == 0) {
continue; continue;
@@ -2114,7 +2114,7 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee
gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL); gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL);
esp_err_t err = ESP_OK; esp_err_t err = ESP_OK;
uint64_t invalid_io_mask = gpio_pin_mask & ~SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK; uint64_t invalid_io_mask = gpio_pin_mask & ~SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK;
if (invalid_io_mask != 0) { if (invalid_io_mask != 0) {
for (gpio_num_t gpio_idx = __builtin_ctzll(invalid_io_mask); invalid_io_mask >> gpio_idx; gpio_idx++) { for (gpio_num_t gpio_idx = __builtin_ctzll(invalid_io_mask); invalid_io_mask >> gpio_idx; gpio_idx++) {
if (invalid_io_mask & BIT64(gpio_idx)) { if (invalid_io_mask & BIT64(gpio_idx)) {
@@ -2141,7 +2141,7 @@ esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepslee
return err; return err;
} }
#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED #endif //SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
esp_err_t esp_sleep_enable_gpio_wakeup(void) esp_err_t esp_sleep_enable_gpio_wakeup(void)
{ {
components/esp_hw_support/test_apps/wakeup_tests/main/src/io_wakeup_cmd.c
+4 -4
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Unlicense OR CC0-1.0 * SPDX-License-Identifier: Unlicense OR CC0-1.0
*/ */
@@ -142,7 +142,7 @@ static void register_ext1_wakeup(void)
} }
#endif #endif
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
static struct { static struct {
struct arg_int *pin; struct arg_int *pin;
struct arg_int *level; struct arg_int *level;
@@ -383,7 +383,7 @@ static int process_get_wakeup_cause(int argc, char **argv)
if (causes & BIT(ESP_SLEEP_WAKEUP_GPIO)) { if (causes & BIT(ESP_SLEEP_WAKEUP_GPIO)) {
if (esp_reset_reason() == ESP_RST_DEEPSLEEP) { if (esp_reset_reason() == ESP_RST_DEEPSLEEP) {
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
uint64_t wakeup_pin_mask = esp_sleep_get_gpio_wakeup_status(); uint64_t wakeup_pin_mask = esp_sleep_get_gpio_wakeup_status();
if (wakeup_pin_mask != 0) { if (wakeup_pin_mask != 0) {
int pin = __builtin_ffsll(wakeup_pin_mask) - 1; int pin = __builtin_ffsll(wakeup_pin_mask) - 1;
@@ -440,7 +440,7 @@ void register_io_wakeup_cmd(void)
#endif #endif
register_gpio_control(); register_gpio_control();
register_gpio_wakeup(); register_gpio_wakeup();
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP #if SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
register_rtcio_wakeup(); register_rtcio_wakeup();
#endif #endif
register_get_wakeup_cause(); register_get_wakeup_cause();
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -291,7 +291,7 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
@@ -303,11 +303,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 20 default 20
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 6 default 6
components/soc/esp32c2/include/soc/soc_caps.h
+6 -6
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@@ -126,21 +126,21 @@
#define SOC_GPIO_PIN_COUNT 21 #define SOC_GPIO_PIN_COUNT 21
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as HP peripheral powerdown-ed sleep wakeup pins)
// Force hold is a new function of ESP32-C2 // Force hold is a new function of ESP32-C2
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32-C2 can support chip deep sleep wakeup // GPIO0~5 on ESP32-C2 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1) #define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 20 #define SOC_GPIO_IN_RANGE_MAX 20
#define SOC_GPIO_OUT_RANGE_MAX 20 #define SOC_GPIO_OUT_RANGE_MAX 20
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_20)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000001FFFC0ULL
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -387,7 +387,7 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
@@ -399,11 +399,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 21 default 21
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 6 default 6
components/soc/esp32c3/include/soc/soc_caps.h
+6 -6
View File
@@ -165,21 +165,21 @@
#define SOC_GPIO_PIN_COUNT 22 #define SOC_GPIO_PIN_COUNT 22
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as deep-sleep wakeup pins) // Target has no full RTC IO subsystem, GPIO0~5 remain RTC function (powered by VDD3V3_RTC, and can be used as HP peripheral powerdown-ed wakeup pins)
// Force hold is a new function of ESP32-C3 // Force hold is a new function of ESP32-C3
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup // GPIO0~5 on ESP32C3 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1) #define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21 #define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21 #define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFFC0ULL
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -559,7 +559,7 @@ config SOC_GPIO_SUPPORT_ETM
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
@@ -575,11 +575,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 28 default 28
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 7 default 7
components/soc/esp32c5/include/soc/soc_caps.h
+5 -4
View File
@@ -220,8 +220,9 @@
#define SOC_GPIO_SUPPORT_ETM 1 #define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem // Target has the full LP IO subsystem
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup // GPIO0~7 on ESP32C5 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage // LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -231,8 +232,8 @@
#define SOC_GPIO_IN_RANGE_MAX 28 #define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28 #define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -479,7 +479,7 @@ config SOC_GPIO_SUPPORT_ETM
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
@@ -495,11 +495,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 30 default 30
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 8 default 8
components/soc/esp32c6/include/soc/soc_caps.h
+5 -4
View File
@@ -195,8 +195,9 @@
#define SOC_GPIO_SUPPORT_ETM 1 #define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem // Target has the full LP IO subsystem
// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup // GPIO0~7 on ESP32C6 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage // LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -206,8 +207,8 @@
#define SOC_GPIO_IN_RANGE_MAX 30 #define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30 #define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (8) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (8)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -443,15 +443,15 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 29 default 29
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 7 default 7
components/soc/esp32c61/include/soc/soc_caps.h
+5 -4
View File
@@ -187,10 +187,11 @@
#define SOC_GPIO_IN_RANGE_MAX 29 #define SOC_GPIO_IN_RANGE_MAX 29
#define SOC_GPIO_OUT_RANGE_MAX 29 #define SOC_GPIO_OUT_RANGE_MAX 29
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup // GPIO0~6 on ESP32C61 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_29)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x3FFFFF80ULL
components/soc/esp32h2/include/soc/soc_caps.h
+1 -1
View File
@@ -224,7 +224,7 @@
// LP IO peripherals have independent clock gating to manage // LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup through EXT1 wake up // GPIO7~14 on ESP32H2 can support chip HP peripheral powerdown-ed sleep wakeup through EXT1 wake up
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1) #define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -339,15 +339,15 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 6 default 6
components/soc/esp32h4/include/soc/soc_caps.h
+4 -3
View File
@@ -220,9 +220,10 @@
// LP IO peripherals have independent clock gating to manage // LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP 1 #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (6) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_6~GPIO_NUM_39)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1)) #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK (SOC_GPIO_VALID_GPIO_MASK & ~((1ULL<<6) - 1))
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -679,7 +679,7 @@ config SOC_GPIO_SUPPORT_ETM
bool bool
default y default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool bool
default y default y
@@ -703,11 +703,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int int
default 54 default 54
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int int
default 0 default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int int
default 16 default 16
components/soc/esp32p4/include/soc/soc_caps.h
+5 -4
View File
@@ -254,8 +254,9 @@
// Target has the full LP IO subsystem // Target has the full LP IO subsystem
// GPIO0~15 on ESP32P4 can support chip deep sleep wakeup // GPIO0~15 on ESP32P4 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
#define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1)
// LP IO peripherals have independent clock gating to manage // LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) #define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -266,8 +267,8 @@
#define SOC_GPIO_IN_RANGE_MAX 54 #define SOC_GPIO_IN_RANGE_MAX 54
#define SOC_GPIO_OUT_RANGE_MAX 54 #define SOC_GPIO_OUT_RANGE_MAX 54
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | 0xFFFF) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | 0xFFFF)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (16) #define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (16)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54) // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_16~GPIO_NUM_54)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x007FFFFFFFFF0000ULL
docs/en/api-reference/system/sleep_modes.rst
+3 -3
View File
@@ -308,13 +308,13 @@ RTC peripherals or RTC memories do not need to be powered on during sleep in thi
.. note:: .. note::
.. only:: SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， to continue using :cpp:func:`gpio_wakeup_enable` for GPIO wakeup, you need to first call :cpp:func:`rtc_gpio_init` and :cpp:func:`rtc_gpio_set_direction`, setting the RTCIO to input mode. In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， to continue using :cpp:func:`gpio_wakeup_enable` for GPIO wakeup, you need to first call :cpp:func:`rtc_gpio_init` and :cpp:func:`rtc_gpio_set_direction`, setting the RTCIO to input mode.
Alternatively，you can use :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` directly in that condition for GPIO wakeup, because the digital IO power domain is being powered off, where the situation is the same as entering Deep-sleep. Alternatively，you can use :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` directly in that condition for GPIO wakeup, because the digital IO power domain is being powered off, where the situation is the same as entering Deep-sleep.
.. only:: not SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: not SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， to continue using :cpp:func:`gpio_wakeup_enable` for GPIO wakeup, you need to first call :cpp:func:`rtc_gpio_init` and :cpp:func:`rtc_gpio_set_direction`, setting the RTCIO to input mode. In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， to continue using :cpp:func:`gpio_wakeup_enable` for GPIO wakeup, you need to first call :cpp:func:`rtc_gpio_init` and :cpp:func:`rtc_gpio_set_direction`, setting the RTCIO to input mode.
@@ -331,7 +331,7 @@ RTC peripherals or RTC memories do not need to be powered on during sleep in thi
.. note:: .. note::
.. only:: SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， you can use :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` directly for GPIO wakeup, because the digital IO power domain is being powered off, where the situation is the same as entering Deep-sleep. In Light-sleep mode, if you set Kconfig option :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`， you can use :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` directly for GPIO wakeup, because the digital IO power domain is being powered off, where the situation is the same as entering Deep-sleep.
docs/zh_CN/api-reference/system/sleep_modes.rst
+3 -3
View File
@@ -308,13 +308,13 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒
.. note:: .. note::
.. only:: SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，为了继续使用 :cpp:func:`gpio_wakeup_enable` 用于 GPIO 唤醒， 需要先调用 :cpp:func:`rtc_gpio_init` 和 :cpp:func:`rtc_gpio_set_direction`，用于设置 RTC IO 为输入模式。 在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，为了继续使用 :cpp:func:`gpio_wakeup_enable` 用于 GPIO 唤醒， 需要先调用 :cpp:func:`rtc_gpio_init` 和 :cpp:func:`rtc_gpio_set_direction`，用于设置 RTC IO 为输入模式。
或者， 可以使用直接调用 :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` 用于 GPIO 唤醒，因为此时 digital IO 的电源域已经被关闭，这个情况类似于进入 Deep-sleep。 或者， 可以使用直接调用 :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` 用于 GPIO 唤醒，因为此时 digital IO 的电源域已经被关闭，这个情况类似于进入 Deep-sleep。
.. only:: not SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: not SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，为了继续使用 :cpp:func:`gpio_wakeup_enable` 用于 GPIO 唤醒， 需要先调用 :cpp:func:`rtc_gpio_init` 和 :cpp:func:`rtc_gpio_set_direction`，用于设置 RTC IO 为输入模式。 在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，为了继续使用 :cpp:func:`gpio_wakeup_enable` 用于 GPIO 唤醒， 需要先调用 :cpp:func:`rtc_gpio_init` 和 :cpp:func:`rtc_gpio_set_direction`，用于设置 RTC IO 为输入模式。
@@ -331,7 +331,7 @@ RTC 控制器中内嵌定时器，可用于在预定义的时间到达后唤醒
.. note:: .. note::
.. only:: SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP .. only:: SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，可以使用直接调用 :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` 用于 GPIO 唤醒，因为此时 digital IO 的电源域会被断电，行为与进入 Deep-sleep 模式时相同。 在 Light-sleep 模式下，如果设置 Kconfig 选项 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，可以使用直接调用 :cpp:func:`esp_deep_sleep_enable_gpio_wakeup` 用于 GPIO 唤醒，因为此时 digital IO 的电源域会被断电，行为与进入 Deep-sleep 模式时相同。
examples/system/deep_sleep/main/Kconfig.projbuild
+1 -1
View File
@@ -251,7 +251,7 @@ menu "Example Configuration"
config EXAMPLE_GPIO_WAKEUP config EXAMPLE_GPIO_WAKEUP
bool "Enable wakeup from GPIO" bool "Enable wakeup from GPIO"
default y default y
depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP depends on SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
help help
This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly This option enables wake up from GPIO. Be aware that if you use low level to trigger wakeup, we strongly
recommend you to connect external pull-up resistance. recommend you to connect external pull-up resistance.