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change(soc): rename peripheral powerdowned sleep wakeable IO soc_caps

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rename SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
rename SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
rename SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP to SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
This commit is contained in:
wuzhenghui
2026-02-01 12:16:20 +08:00
committed by Jack
parent afa266ebd6
commit 85601ccb69
29 changed files with 98 additions and 92 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+3 -3
View File
@@ -559,7 +559,7 @@ config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
config SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
bool
default y
@@ -575,11 +575,11 @@ config SOC_GPIO_OUT_RANGE_MAX
int
default 28
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
int
default 0
config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
int
default 7
components/soc/esp32c5/include/soc/soc_caps.h
+5 -4
View File
@@ -220,8 +220,9 @@
#define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// GPIO0~7 on ESP32C5 can support chip HP peripheral powerdown-ed sleep wakeup
#define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1)
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
@@ -231,8 +232,8 @@
#define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF80ULL