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feat(ble): support adv fast tx feature on ESP32-C6 and ESP32-H2
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@@ -6,17 +6,27 @@ entries:
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entries:
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.high_perf_code_iram1+
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[sections:adv_fast_execute_code_iram_text]
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entries:
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.adv_fast_execute_code_iram1+
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[scheme:bt_default]
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entries:
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bt_bss -> dram0_bss
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bt_common -> dram0_bss
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data -> dram0_data
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high_perf_iram_text -> iram0_text
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if BT_CTRL_RUN_IN_FLASH_ONLY = y:
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bt_iram_text -> flash_text
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else:
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bt_iram_text -> iram0_text
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if BT_LE_CTRL_ADV_FAST_TX_EN = y:
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adv_fast_execute_code_iram_text -> iram0_text
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else:
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adv_fast_execute_code_iram_text -> flash_text
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# For the following fragments, order matters for
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# 'ALIGN(4) ALIGN(4, post) SURROUND(sym)', which generates:
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#
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