Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-03 03:31:41 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(hal): graudate the adc/dac hal driver into a new component

Browse Source
This commit is contained in:
laokaiyao
2025-12-11 10:27:00 +08:00
parent 55537c99db
commit 841cb4caa1
64 changed files with 583 additions and 450 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hal_ana_conv/include/hal/adc_hal.h
+191
View File
@@ -0,0 +1,191 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "esp_err.h"
#include "soc/soc_caps.h"
#include "hal/dma_types.h"
#include "hal/adc_types.h"
#include "hal/adc_hal_common.h"
#if SOC_ADC_DMA_SUPPORTED
#include "hal/adc_ll.h"
#endif
#if SOC_IS(ESP32S2)
//ADC utilises SPI3 DMA on ESP32S2
#include "hal/spi_ll.h"
#endif
#if SOC_IS(ESP32)
//ADC utilises I2S0 DMA on ESP32
#include "hal/i2s_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_IS(ESP32)
#define ADC_HAL_DMA_I2S_HOST 0
#endif
/**
* @brief Enum for DMA descriptor status
*/
typedef enum adc_hal_dma_desc_status_t {
ADC_HAL_DMA_DESC_VALID = 0, ///< This DMA descriptor is written by HW already
ADC_HAL_DMA_DESC_WAITING = 1, ///< This DMA descriptor is not written by HW yet
ADC_HAL_DMA_DESC_NULL = 2 ///< This DMA descriptor is NULL
} adc_hal_dma_desc_status_t;
/**
* @brief Configuration of the HAL
*/
typedef struct adc_hal_dma_config_t {
uint32_t eof_desc_num; ///< Number of dma descriptors that is eof
uint32_t eof_step; ///< Number of linked descriptors that is one eof
uint32_t eof_num; ///< Bytes between 2 in_suc_eof interrupts
} adc_hal_dma_config_t;
/**
* @brief Context of the HAL
*/
typedef struct adc_hal_dma_ctx_t {
/**< this needs to be malloced by the driver layer first */
dma_descriptor_t *rx_desc; ///< DMA descriptors
/**< these will be assigned by hal layer itself */
dma_descriptor_t desc_dummy_head; ///< Dummy DMA descriptor for ``cur_desc_ptr`` to start
dma_descriptor_t *cur_desc_ptr; ///< Pointer to the current descriptor
/**< these need to be configured by `adc_hal_dma_config_t` via driver layer*/
uint32_t eof_desc_num; ///< Number of dma descriptors that is eof
uint32_t eof_step; ///< Number of linked descriptors that is one eof
uint32_t eof_num; ///< Words between 2 in_suc_eof interrupts
} adc_hal_dma_ctx_t;
typedef struct adc_hal_digi_ctrlr_cfg_t {
uint32_t adc_pattern_len; //total pattern item number, including ADC1 and ADC2
adc_digi_pattern_config_t *adc_pattern; //pattern item
uint32_t sample_freq_hz; //ADC sample frequency
adc_digi_convert_mode_t conv_mode; //controller work mode
uint32_t bit_width; //output data width
adc_continuous_clk_src_t clk_src; ///< Clock source
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
} adc_hal_digi_ctrlr_cfg_t;
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
/**
* Set adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @prarm cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_set_cct(cct) adc_ll_pwdet_set_cct(cct)
/**
* Get adc cct for PWDET controller.
*
* @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
* @return cct Range: 0 ~ 7.
*/
#define adc_hal_pwdet_get_cct() adc_ll_pwdet_get_cct()
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* @brief Initialize the HW
*
* @param hal Context of the HAL
*/
void adc_hal_digi_init(adc_hal_dma_ctx_t *hal);
/**
* Digital controller deinitialization.
*
*/
void adc_hal_digi_deinit(void);
/**
* @brief Initialize the hal context
*
* @param hal Context of the HAL
* @param config Configuration of the HAL
*/
void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *config);
/**
* Setting the digital controller.
*
* @param hal Context of the HAL
* @param cfg Pointer to digital controller parameter.
*/
void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg);
/**
* @brief Link DMA descriptor
*
* @param hal Context of the HAL
* @param data_buf Pointer to the data buffer, the length should be multiple of ``desc_max_num`` and ``eof_num`` in ``adc_hal_dma_ctx_t``
*/
void adc_hal_digi_dma_link(adc_hal_dma_ctx_t *hal, uint8_t *data_buf);
/**
* @brief Get the ADC reading result
*
* @param hal Context of the HAL
* @param eof_desc_addr The last descriptor that is finished by HW. Should be got from DMA
* @param[out] buffer ADC reading result buffer
* @param[out] len ADC reading result len
*
* @return See ``adc_hal_dma_desc_status_t``
*/
adc_hal_dma_desc_status_t adc_hal_get_reading_result(adc_hal_dma_ctx_t *hal, const intptr_t eof_desc_addr, uint8_t **buffer, uint32_t *len);
/**
* @brief Enable or disable ADC digital controller
*
* @param enable true to enable, false to disable
*/
void adc_hal_digi_enable(bool enable);
/**
* @brief Enable pr disable output data to DMA from adc digital controller.
*
* @param enable true to enable, false to disable
*/
void adc_hal_digi_connect(bool enable);
/**
* @brief Reset adc digital controller.
*/
void adc_hal_digi_reset(void);
#if ADC_LL_WORKAROUND_CLEAR_EOF_COUNTER
/**
* @brief Clear the ADC sample counter
*/
void adc_hal_digi_clr_eof(void);
#endif
/**
* @brief Set ADC monitor with high and low thresholds, and will enable the interrupts accordingly
*
* @param monitor_id Monitor to configure
* @param adc_n Which ADC unit will be monitored
* @param adc_ch Which ADC channel will be monitored
* @param h_thres High threshold (disable if < 0)
* @param l_thres Low threshold (disable if < 0)
*/
void adc_hal_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t adc_ch, int32_t h_thres, int32_t l_thres);
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/adc_hal_common.h
+96
View File
@@ -0,0 +1,96 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* This header file is only for hardware abstract concepts and APIs
* used by both ADC RTC controller and Digital controller
*/
/**
* ADC work mode
*/
typedef enum adc_hal_work_mode_t {
ADC_HAL_SINGLE_READ_MODE,
ADC_HAL_CONTINUOUS_READ_MODE,
ADC_HAL_PWDET_MODE,
ADC_HAL_LP_MODE,
} adc_hal_work_mode_t;
/**
* Set ADC work mode
*
* @param unit ADC unit
* @param work_mode see `adc_hal_work_mode_t`
*/
void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode);
#if SOC_ADC_ARBITER_SUPPORTED
//No ADC2 controller arbiter on ESP32
/**
* Config ADC2 module arbiter.
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
* the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
*
* @note Only ADC2 support arbiter.
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
* @note Default priority: Wi-Fi > RTC > Digital;
*
* @param config Refer to ``adc_arbiter_t``.
*/
void adc_hal_arbiter_config(adc_arbiter_t *config);
#endif //#if SOC_ADC_ARBITER_SUPPORTED
/*---------------------------------------------------------------
ADC calibration setting
---------------------------------------------------------------*/
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
/**
* @brief Initialize default parameter for the calibration block.
*
* @param adc_n ADC index number
*/
void adc_hal_calibration_init(adc_unit_t adc_n);
/**
* Set the calibration result (initial data) to ADC.
*
* @note Different ADC units and different attenuation options use different calibration data (initial data).
*
* @param adc_n ADC index number.
* @param param the calibration parameter to configure
*/
void adc_hal_set_calibration_param(adc_unit_t adc_n, uint32_t param);
/**
* Calibrate the ADC using internal connections.
*
* @note Different ADC units and different attenuation options use different calibration data (initial data).
*
* @param adc_n ADC index number.
* @param atten ADC attenuation
* @param internal_gnd true: Disconnect from the IO port and use the internal GND as the calibration voltage.
* false: Use IO external voltage as calibration voltage.
*
* @return
* - The calibration result (initial data) to ADC, use `adc_hal_set_calibration_param` to set.
*/
uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool internal_gnd);
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/adc_oneshot_hal.h
+88
View File
@@ -0,0 +1,88 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "hal/adc_types.h"
#include "hal/adc_hal_common.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct sens_dev_t *adc_oneshot_soc_handle_t;
typedef struct adc_oneshot_hal_cfg_t {
adc_unit_t unit; ///< ADC unit
adc_hal_work_mode_t work_mode; ///< ADC work mode
adc_oneshot_clk_src_t clk_src; ///< Clock source
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
bool disable_dac_output; ///< Whether to disable DAC output, only for chips supporting DAC
} adc_oneshot_hal_cfg_t;
/**
* ADC channel configuration
*/
typedef struct adc_oneshot_hal_chan_cfg_t {
adc_atten_t atten; ///< ADC attenuation
adc_bitwidth_t bitwidth; ///< ADC conversion result bits
} adc_oneshot_hal_chan_cfg_t;
/**
* Context of the ADC unit, should be maintained by both the driver and the HAL.
*/
typedef struct adc_oneshot_hal_ctx_t {
/* These should be configured by driver, dou't modify these directly in hal*/
adc_oneshot_soc_handle_t dev; ///< ADC SoC layer handle
adc_unit_t unit; ///< ADC unit
adc_hal_work_mode_t work_mode; ///< ADC work mode
adc_oneshot_hal_chan_cfg_t chan_configs[SOC_ADC_MAX_CHANNEL_NUM]; ///< ADC configurations per channel
adc_oneshot_clk_src_t clk_src; ///< Clock source
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
bool disable_dac_output; ///< Whether to disable DAC output, only for chips supporting DAC
} adc_oneshot_hal_ctx_t;
/**
* Initialise the context
*
* @param hal ADC Oneshot Hal context
* @param config ADC Oneshot Hal init config
*/
void adc_oneshot_hal_init(adc_oneshot_hal_ctx_t *hal, const adc_oneshot_hal_cfg_t *config);
/**
* Prepare ADC Oneshot hal context
*
* @param hal ADC Oneshot Hal context
* @param config ADC Oneshot Hal configuration
* @param chan ADC Channel
*/
void adc_oneshot_hal_channel_config(adc_oneshot_hal_ctx_t *hal, const adc_oneshot_hal_chan_cfg_t *config, adc_channel_t chan);
/**
* Set ADC Oneshot mode required registers
*
* @param hal ADC Oneshot Hal context
* @param channel ADC Channel
*/
void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel);
/**
* Start ADC conversion in Oneshot mode and get the raw result
*
* @param hal ADC Oneshot Hal context
* @param[out] out_raw ADC oneshot conversion raw result
*
* @return
* - true: ADC raw result is valid
* - false: ADC raw result is invalid
*/
bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw);
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/adc_periph.h
+30
View File
@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#include "soc/soc_caps.h"
#if SOC_ADC_SUPPORTED
#include "soc/adc_channel.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* Store IO number corresponding to the ADC channel number.
*
* @value
* - >=0 : GPIO number index.
* - -1 : Not support.
*/
extern const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM];
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/adc_types.h
+248
View File
@@ -0,0 +1,248 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ADC unit
*/
typedef enum {
ADC_UNIT_1, ///< SAR ADC 1
ADC_UNIT_2, ///< SAR ADC 2
} adc_unit_t;
/**
* @brief ADC channels
*/
typedef enum {
ADC_CHANNEL_0, ///< ADC channel
ADC_CHANNEL_1, ///< ADC channel
ADC_CHANNEL_2, ///< ADC channel
ADC_CHANNEL_3, ///< ADC channel
ADC_CHANNEL_4, ///< ADC channel
ADC_CHANNEL_5, ///< ADC channel
ADC_CHANNEL_6, ///< ADC channel
ADC_CHANNEL_7, ///< ADC channel
ADC_CHANNEL_8, ///< ADC channel
ADC_CHANNEL_9, ///< ADC channel
ADC_CHANNEL_10, ///< ADC channel
} adc_channel_t;
/**
* @brief ADC attenuation parameter. Different parameters determine the range of the ADC.
*/
typedef enum {
ADC_ATTEN_DB_0 = 0, ///<No input attenuation, ADC can measure up to approx.
ADC_ATTEN_DB_2_5 = 1, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 2.5 dB
ADC_ATTEN_DB_6 = 2, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 6 dB
ADC_ATTEN_DB_12 = 3, ///<The input voltage of ADC will be attenuated extending the range of measurement by about 12 dB
} adc_atten_t;
/**
* @brief ADC bitwidth
*/
typedef enum {
ADC_BITWIDTH_DEFAULT = 0, ///< Default ADC output bits, max supported width will be selected
ADC_BITWIDTH_9 = 9, ///< ADC output width is 9Bit
ADC_BITWIDTH_10 = 10, ///< ADC output width is 10Bit
ADC_BITWIDTH_11 = 11, ///< ADC output width is 11Bit
ADC_BITWIDTH_12 = 12, ///< ADC output width is 12Bit
ADC_BITWIDTH_13 = 13, ///< ADC output width is 13Bit
} adc_bitwidth_t;
/**
* @brief ADC ULP working mode
*
* This decides the controller that controls ADC when in low power mode.
* Set `ADC_ULP_MODE_DISABLE` for normal mode.
*/
typedef enum {
ADC_ULP_MODE_DISABLE = 0, ///< ADC ULP mode is disabled
ADC_ULP_MODE_FSM = 1, ///< ADC is controlled by ULP FSM
ADC_ULP_MODE_RISCV = 2, ///< ADC is controlled by ULP RISCV
#if SOC_LP_ADC_SUPPORTED
ADC_ULP_MODE_LP_CORE = 3, ///< ADC is controlled by LP Core
#endif // SOC_LP_ADC_SUPPORTED
} adc_ulp_mode_t;
/**
* @brief ADC digital controller (DMA mode) work mode.
*/
typedef enum {
ADC_CONV_SINGLE_UNIT_1 = 1, ///< Only use ADC1 for conversion
ADC_CONV_SINGLE_UNIT_2 = 2, ///< Only use ADC2 for conversion
ADC_CONV_BOTH_UNIT = 3, ///< Use Both ADC1 and ADC2 for conversion simultaneously
ADC_CONV_ALTER_UNIT = 7, ///< Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
} adc_digi_convert_mode_t;
/**
* @brief ADC digital controller (DMA mode) output data format option.
*/
typedef enum {
ADC_DIGI_OUTPUT_FORMAT_TYPE1, ///< See `adc_digi_output_data_t.type1`
ADC_DIGI_OUTPUT_FORMAT_TYPE2, ///< See `adc_digi_output_data_t.type2`
} adc_digi_output_format_t;
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
typedef soc_periph_adc_digi_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses digital controller
typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller
#elif SOC_ADC_RTC_CTRL_SUPPORTED
typedef soc_periph_adc_rtc_clk_src_t adc_oneshot_clk_src_t; ///< Clock source type of oneshot mode which uses RTC controller
typedef soc_periph_adc_digi_clk_src_t adc_continuous_clk_src_t; ///< Clock source type of continuous mode which uses digital controller
#else
typedef int adc_oneshot_clk_src_t; ///< Default type
typedef int adc_continuous_clk_src_t; ///< Default type
#endif
/**
* @brief ADC digital controller pattern configuration
*/
typedef struct {
uint8_t atten; ///< Attenuation of this ADC channel
uint8_t channel; ///< ADC channel
uint8_t unit; ///< ADC unit
uint8_t bit_width; ///< ADC output bit width
} adc_digi_pattern_config_t;
/**
* @brief ADC IIR Filter ID
*/
typedef enum {
ADC_DIGI_IIR_FILTER_0, ///< Filter 0
ADC_DIGI_IIR_FILTER_1, ///< Filter 1
} adc_digi_iir_filter_t;
/**
* @brief IIR Filter Coefficient
*/
typedef enum {
ADC_DIGI_IIR_FILTER_COEFF_2, ///< The filter coefficient is 2
ADC_DIGI_IIR_FILTER_COEFF_4, ///< The filter coefficient is 4
ADC_DIGI_IIR_FILTER_COEFF_8, ///< The filter coefficient is 8
ADC_DIGI_IIR_FILTER_COEFF_16, ///< The filter coefficient is 16
ADC_DIGI_IIR_FILTER_COEFF_32, ///< The filter coefficient is 32
ADC_DIGI_IIR_FILTER_COEFF_64, ///< The filter coefficient is 64
} adc_digi_iir_filter_coeff_t;
/*---------------------------------------------------------------
ADC Monitor
---------------------------------------------------------------*/
/**
* @brief ADC monitor (continuous mode) ID
*/
typedef enum {
ADC_MONITOR_0, ///< The monitor index 0.
ADC_MONITOR_1, ///< The monitor index 1.
} adc_monitor_id_t;
/**
* @brief Monitor config/event mode type
*/
typedef enum {
ADC_MONITOR_MODE_HIGH = 0, ///< ADC raw_result > threshold value, monitor interrupt will be generated.
ADC_MONITOR_MODE_LOW, ///< ADC raw_result < threshold value, monitor interrupt will be generated.
} adc_monitor_mode_t;
/*---------------------------------------------------------------
Output Format
---------------------------------------------------------------*/
#if SOC_IS(ESP32) || SOC_IS(ESP32S2)
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
* @note ESP32: Only `type1` is valid. ADC2 does not support DMA mode.
* @note ESP32-S2: Member `channel` can be used to judge the validity of the ADC data,
* because the role of the arbiter may get invalid ADC data.
*/
typedef struct {
union {
struct {
uint16_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint16_t channel: 4; /*!<ADC channel index info. */
} type1; /*!<ADC type1 */
struct {
uint16_t data: 11; /*!<ADC real output data info. Resolution: 11 bit. */
uint16_t channel: 4; /*!<ADC channel index info. For ESP32-S2:
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint16_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
} type2; /*!<When the configured output format is 11bit.*/
uint16_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#elif SOC_IS(ESP32C3) || SOC_IS(ESP32C2)
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*/
typedef struct {
union {
struct {
uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint32_t reserved12: 1; /*!<Reserved12. */
uint32_t channel: 3; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
uint32_t reserved17_31: 15; /*!<Reserved17. */
} type2; /*!<When the configured output format is 12bit. */
uint32_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#elif SOC_IS(ESP32S3) || SOC_IS(ESP32P4)
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*/
typedef struct {
union {
struct {
uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint32_t reserved12: 1; /*!<Reserved12. */
uint32_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint32_t unit: 1; /*!<ADC unit index info. 0: ADC1; 1: ADC2. */
uint32_t reserved17_31: 14; /*!<Reserved17. */
} type2; /*!<When the configured output format is 12bit. */
uint32_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#elif SOC_IS(ESP32C6) || SOC_IS(ESP32H2) || SOC_IS(ESP32C5) || SOC_IS(ESP32C61)
/**
* @brief ADC digital controller (DMA mode) output data format.
* Used to analyze the acquired ADC (DMA) data.
*/
typedef struct {
union {
struct {
uint32_t data: 12; /*!<ADC real output data info. Resolution: 12 bit. */
uint32_t reserved12: 1; /*!<Reserved12. */
uint32_t channel: 4; /*!<ADC channel index info.
If (channel < ADC_CHANNEL_MAX), The data is valid.
If (channel > ADC_CHANNEL_MAX), The data is invalid. */
uint32_t reserved17_31: 15; /*!<Reserved 17-31. */
} type2; /*!<When the configured output format is 12bit. */
uint32_t val; /*!<Raw data value */
};
} adc_digi_output_data_t;
#endif
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/adc_types_private.h
+51
View File
@@ -0,0 +1,51 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_ADC_ARBITER_SUPPORTED
/*---------------------------------------------------------------
Arbiter
---------------------------------------------------------------*/
/**
* @brief ADC arbiter work mode option.
*/
typedef enum {
ADC_ARB_MODE_SHIELD, ///< Force shield arbiter, Select the highest priority controller to work
ADC_ARB_MODE_FIX, ///< Fixed priority switch controller mode
ADC_ARB_MODE_LOOP, ///< Loop priority switch controller mode. Each controller has the same priority, and the arbiter will switch to the next controller after the measurement is completed
} adc_arbiter_mode_t;
/**
* @brief ADC arbiter work mode and priority setting.
*
* @note Only ADC2 support arbiter.
*/
typedef struct {
adc_arbiter_mode_t mode; ///< Refer to ``adc_arbiter_mode_t``
uint8_t rtc_pri; ///< RTC controller priority. Range: 0 ~ 2
uint8_t dig_pri; ///< Digital controller priority. Range: 0 ~ 2
uint8_t pwdet_pri; ///< Wi-Fi controller priority. Range: 0 ~ 2
} adc_arbiter_t;
/**
* @brief ADC arbiter default configuration.
*/
#define ADC_ARBITER_CONFIG_DEFAULT() { \
.mode = ADC_ARB_MODE_FIX, \
.rtc_pri = 1, \
.dig_pri = 0, \
.pwdet_pri = 2, \
}
#endif //#if SOC_ADC_ARBITER_SUPPORTED
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/dac_periph.h
+29
View File
@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if SOC_DAC_SUPPORTED
typedef struct {
const uint8_t dac_channel_io_num[SOC_DAC_CHAN_NUM];
} dac_signal_conn_t;
extern const dac_signal_conn_t dac_periph_signal;
#endif // SOC_DAC_SUPPORTED
#ifdef __cplusplus
}
#endif
components/esp_hal_ana_conv/include/hal/dac_types.h
+40
View File
@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
DAC_CHAN_0 = 0, /*!< DAC channel 0 is GPIO25(ESP32) / GPIO17(ESP32S2) */
DAC_CHAN_1 = 1, /*!< DAC channel 1 is GPIO26(ESP32) / GPIO18(ESP32S2) */
} dac_channel_t;
/**
* @brief The attenuation of the amplitude of the cosine wave generator. The max amplitude is VDD3P3_RTC.
*/
typedef enum {
DAC_COSINE_ATTEN_DEFAULT = 0x0, /*!< No attenuation to the DAC cosine wave amplitude. Default. */
DAC_COSINE_ATTEN_DB_0 = 0x0, /*!< Original amplitude of the DAC cosine wave, equals to DAC_COSINE_ATTEN_DEFAULT */
DAC_COSINE_ATTEN_DB_6 = 0x1, /*!< 1/2 amplitude of the DAC cosine wave */
DAC_COSINE_ATTEN_DB_12 = 0x2, /*!< 1/4 amplitude of the DAC cosine wave */
DAC_COSINE_ATTEN_DB_18 = 0x3, /*!< 1/8 amplitude of the DAC cosine wave */
} dac_cosine_atten_t;
/**
* @brief Set the phase of the cosine wave generator output.
* @note Only 0 or 180 are supported,
* it will be set to 0 as default if configured to an unsupported phase.
*/
typedef enum {
DAC_COSINE_PHASE_0 = 0x02, /*!< Phase shift +0° */
DAC_COSINE_PHASE_180 = 0x03, /*!< Phase shift +180° */
} dac_cosine_phase_t;
#ifdef __cplusplus
}
#endif