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Merge branch 'feat/lcd_use_apll_clock' into 'master'

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refactor(clk_tree): use general api to enable the clk

Closes IDF-11478 and IDF-12972

See merge request espressif/esp-idf!35952
This commit is contained in:
Chen Ji Chang
2026-04-20 22:12:01 +08:00
parent b43ee27ebc 6e206dd173
commit 83e7b11716
57 changed files with 1180 additions and 694 deletions
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components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h
+2 -2
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@@ -51,8 +51,8 @@
#define CLK_LL_APLL_MULTIPLIER_MAX_HZ (500000000) // 500 MHz
/* APLL output frequency range */
#define CLK_LL_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define CLK_LL_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'esp_clk_tree_apll_freq_set' for the calculation
#define CLK_LL_APLL_MAX_HZ (125000000) // 125MHz, refer to 'esp_clk_tree_apll_freq_set' for the calculation
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
.dac = 7, \