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fix(esp_rom): fix RTC_SLEEP_MODE_REG addr mismatch

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This commit is contained in:
hebinglin
2026-05-21 15:34:38 +08:00
parent f4f8bbd8bf
commit 83813904f4
3 changed files with 8 additions and 8 deletions
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components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
+2 -2
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@@ -50,8 +50,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
* LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
*************************************************************************************
*/
components/esp_rom/esp32c61/include/esp32c61/rom/rtc.h
+2 -2
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@@ -51,8 +51,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG RTC fix us, low 32 bits
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
* LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
*************************************************************************************
*
* Since esp32c61 does not support RTC mem, so use LP_AON store regs to record rtc time:
components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h
+4 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -52,8 +52,8 @@ extern "C" {
* LP_AON_STORE5_REG FAST_RTC_MEMORY_LENGTH
* LP_AON_STORE6_REG FAST_RTC_MEMORY_ENTRY
* LP_AON_STORE7_REG FAST_RTC_MEMORY_CRC
* LP_AON_STORE8_REG Store light sleep wake stub addr
* LP_AON_STORE9_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
* LP_AON_STORE8_REG Store light sleep wake stub addr (mask bit[1:0])
* LP_AON_STORE8_REG Store the sleep mode at bit[0] (0:light sleep 1:deep sleep)
*************************************************************************************
*/
#define RTC_FIX_US_HIGH_REG LP_AON_STORE0_REG
@@ -66,7 +66,7 @@ extern "C" {
#define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG
#define RTC_FIX_US_LOW_REG LP_AON_STORE7_REG
#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG LP_AON_STORE8_REG
#define SLEEP_MODE_REG LP_AON_STORE9_REG
#define SLEEP_MODE_REG LP_AON_STORE8_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.