Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(sdm): enhance the thread safety

Browse Source
This commit is contained in:
morris
2025-08-11 10:13:57 +08:00
parent e58562e030
commit 83512e3e7c
63 changed files with 504 additions and 579 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-16
View File
@@ -1499,22 +1499,6 @@ config SOC_ECDSA_USES_MPI
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3
components/soc/esp32p4/include/soc/clk_tree_defs.h
-13
View File
@@ -230,19 +230,6 @@ typedef enum {
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
#if SOC_CLK_TREE_SUPPORTED
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
#else
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32p4/include/soc/soc_caps.h
-6
View File
@@ -555,12 +555,6 @@
#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
#define SOC_ECDSA_USES_MPI (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))
components/soc/esp32p4/include/soc/soc_caps_full.h
+4
View File
@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance
components/soc/esp32p4/sdm_periph.c
+29 -26
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,31 +7,34 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
},
[4] = {
GPIO_SD4_OUT_IDX
},
[5] = {
GPIO_SD5_OUT_IDX
},
[6] = {
GPIO_SD6_OUT_IDX
},
[7] = {
GPIO_SD7_OUT_IDX
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
.sig_id_matrix = GPIO_SD3_OUT_IDX
},
[4] = {
.sig_id_matrix = GPIO_SD4_OUT_IDX
},
[5] = {
.sig_id_matrix = GPIO_SD5_OUT_IDX
},
[6] = {
.sig_id_matrix = GPIO_SD6_OUT_IDX
},
[7] = {
.sig_id_matrix = GPIO_SD7_OUT_IDX
}
}
}
};