Merge branch 'feat/p4_eco5_real_chip_v5.4' into 'release/v5.4'

p4: p4 eco5 real chip (v5.4)

See merge request espressif/esp-idf!42063

components/esp_system/port/cpu_start.c

@@ -121,13 +121,13 @@
 #include "esp_private/startup_internal.h"
 #include "esp_private/system_internal.h"
 
-#if SOC_MEM_NON_CONTIGUOUS_SRAM
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _bss_start_low, _bss_start_high;
 extern int _bss_end_low, _bss_end_high;
 #else
 extern int _bss_start;
 extern int _bss_end;
-#endif // SOC_MEM_NON_CONTIGUOUS_SRAM
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _rtc_bss_start;
 extern int _rtc_bss_end;
 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
@@ -431,12 +431,12 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif
 
     //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
-#if SOC_MEM_NON_CONTIGUOUS_SRAM
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     memset(&_bss_start_low, 0, (&_bss_end_low - &_bss_start_low) * sizeof(_bss_start_low));
     memset(&_bss_start_high, 0, (&_bss_end_high - &_bss_start_high) * sizeof(_bss_start_high));
 #else
     memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
-#endif // SOC_MEM_NON_CONTIGUOUS_SRAM
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 
 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
     // Clear Bluetooth bss
@@ -523,12 +523,6 @@ void IRAM_ATTR call_start_cpu0(void)
     Cache_Resume_DCache(0);
 #endif // CONFIG_IDF_TARGET_ESP32S3
 
-#if CONFIG_IDF_TARGET_ESP32P4
-    //TODO: IDF-5670, add cache init API
-    extern void esp_config_l2_cache_mode(void);
-    esp_config_l2_cache_mode();
-#endif
-
 #if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
     // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data

components/esp_system/port/soc/esp32p4/Kconfig.cpu

@@ -1,7 +1,8 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
     prompt "CPU frequency"
     default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
-    default ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default ESP_DEFAULT_CPU_FREQ_MHZ_360 if ESP32P4_SELECTS_REV_LESS_V3
+    default ESP_DEFAULT_CPU_FREQ_MHZ_400
     help
         CPU frequency to be set on application startup.
 
@@ -10,9 +11,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
         depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
     config ESP_DEFAULT_CPU_FREQ_MHZ_360
         bool "360 MHz"
+        depends on ESP32P4_SELECTS_REV_LESS_V3
+    config ESP_DEFAULT_CPU_FREQ_MHZ_400
+        bool "400 MHz"
 endchoice
 
 config ESP_DEFAULT_CPU_FREQ_MHZ
     int
     default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
     default 360 if ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default 400 if ESP_DEFAULT_CPU_FREQ_MHZ_400