From e8edbdd80b3590aef6fca52b082eccdd131eed75 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 16 Sep 2026 11:05:33 +0800 Subject: [PATCH] change(esp_hw_support): remove esp_hw_support to pm dependency --- components/esp_hw_support/CMakeLists.txt | 4 +--- .../port/esp32c5/include/soc/rtc.h | 9 +++----- .../esp_hw_support/port/esp32c5/rtc_clk.c | 23 +------------------ .../port/esp32c6/include/soc/rtc.h | 9 +++----- .../esp_hw_support/port/esp32c6/rtc_clk.c | 3 +-- .../port/esp32c61/include/soc/rtc.h | 9 +++----- .../esp_hw_support/port/esp32c61/rtc_clk.c | 3 +-- .../port/esp32h4/include/soc/rtc.h | 9 +++----- .../esp_hw_support/port/esp32h4/rtc_clk.c | 7 +----- components/esp_hw_support/sleep_modem.c | 2 +- components/esp_hw_support/sleep_modes.c | 14 ++++------- 11 files changed, 22 insertions(+), 70 deletions(-) diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index c06029deca0..eda45a381d3 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -114,9 +114,7 @@ if(NOT non_os_build) list(APPEND priv_requires esp_driver_gpio # for GPIO and RTC (by sleep_gpio and sleep_modes) esp_timer esp_hal_touch_sens # for touch sensor wakeup (introduced in sleep_modes.c) - esp_pm) - - list(APPEND priv_requires esp_mm + esp_mm esp_hal_mspi esp_hal_uart ) diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index d7f4d59f076..8d5b1517f14 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -327,17 +327,14 @@ void rtc_clk_cpu_freq_set_xtal(void); #ifndef BOOTLOADER_BUILD /** - * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU + * @brief Release root clock source locked by PMU * * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL * clock, PMU will forcibly lock the root clock source as PLL, when the root * clock source of the software system is selected as PLL, we need to release - * the root clock source locking and switch the root clock source to PLL in the - * sleep process (a critical section). - * - * @param[in] Maximum CPU frequency, in MHz + * the root clock source locking in the sleep process (a critical section). */ -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); +void rtc_clk_modem_pll_lock_release(void); #endif /** diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index 0f302f21d3f..f7769851bda 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -475,29 +475,8 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void) } #ifndef BOOTLOADER_BUILD -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) +void rtc_clk_modem_pll_lock_release(void) { - // IDF-11064 - if (cpu_freq_mhz == 240) { - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); - rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz); - } else if (cpu_freq_mhz == 160) { - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); - rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); - } else {// cpu_freq_mhz is 80 - if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {// (use 240mhz pll if max cpu freq is 240MHz) -#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); - rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz); -#else - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); - rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); -#endif - } else {// (fixed for chip rev. >= ECO3) - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); - rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); - } - } clk_ll_cpu_clk_src_lock_release(); } #endif diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h index c8c6adc1e56..f6fddf5018e 100644 --- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h @@ -346,17 +346,14 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); void rtc_clk_cpu_freq_set_xtal(void); /** - * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU + * @brief Release root clock source locked by PMU * * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL * clock, PMU will forcibly lock the root clock source as PLL, when the root * clock source of the software system is selected as PLL, we need to release - * the root clock source locking and switch the root clock source to PLL in the - * sleep process (a critical section). - * - * @param[in] Maximum CPU frequency, in MHz + * the root clock source locking in the sleep process (a critical section). */ -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); +void rtc_clk_modem_pll_lock_release(void); /** * @brief Get the current APB frequency. diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c index 120261e8589..14ba14d9252 100644 --- a/components/esp_hw_support/port/esp32c6/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c @@ -366,9 +366,8 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void) #endif } -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) +void rtc_clk_modem_pll_lock_release(void) { - rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz); clk_ll_cpu_clk_src_lock_release(); } diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h index e4018c9f15b..9758d2e7fff 100644 --- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h @@ -316,17 +316,14 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); void rtc_clk_cpu_freq_set_xtal(void); /** - * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU + * @brief Release root clock source locked by PMU * * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL * clock, PMU will forcibly lock the root clock source as PLL, when the root * clock source of the software system is selected as PLL, we need to release - * the root clock source locking and switch the root clock source to PLL in the - * sleep process (a critical section). - * - * @param[in] Maximum CPU frequency, in MHz + * the root clock source locking in the sleep process (a critical section). */ -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); +void rtc_clk_modem_pll_lock_release(void); /** * @brief Get the current APB frequency. diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c index fc2fe2202e7..7fa09eaf0ef 100644 --- a/components/esp_hw_support/port/esp32c61/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c @@ -351,9 +351,8 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void) #endif } -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) +void rtc_clk_modem_pll_lock_release(void) { - rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); clk_ll_cpu_clk_src_lock_release(); } diff --git a/components/esp_hw_support/port/esp32h4/include/soc/rtc.h b/components/esp_hw_support/port/esp32h4/include/soc/rtc.h index 1d3bbeca0e0..7800a59f81d 100644 --- a/components/esp_hw_support/port/esp32h4/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32h4/include/soc/rtc.h @@ -285,17 +285,14 @@ void rtc_clk_cpu_freq_set_xtal(void); #endif /** - * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU + * @brief Release root clock source locked by PMU * * wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL * clock, PMU will forcibly lock the root clock source as PLL, when the root * clock source of the software system is selected as PLL, we need to release - * the root clock source locking and switch the root clock source to PLL in the - * sleep process (a critical section). - * - * @param[in] Maximum CPU frequency, in MHz + * the root clock source locking in the sleep process (a critical section). */ -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); +void rtc_clk_modem_pll_lock_release(void); /** * @brief Get the current APB frequency. diff --git a/components/esp_hw_support/port/esp32h4/rtc_clk.c b/components/esp_hw_support/port/esp32h4/rtc_clk.c index efae5d5728e..9d7029d5e59 100644 --- a/components/esp_hw_support/port/esp32h4/rtc_clk.c +++ b/components/esp_hw_support/port/esp32h4/rtc_clk.c @@ -437,13 +437,8 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void) } #endif -void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) +void rtc_clk_modem_pll_lock_release(void) { - if (cpu_freq_mhz == 96 || cpu_freq_mhz == 48) { - rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz); - } else { // cpu_freq_mhz == 64 - rtc_clk_cpu_freq_to_xtal_x2(cpu_freq_mhz, 1); - } clk_ll_cpu_clk_src_lock_release(); } diff --git a/components/esp_hw_support/sleep_modem.c b/components/esp_hw_support/sleep_modem.c index f7c19fac44d..af073ffcb25 100644 --- a/components/esp_hw_support/sleep_modem.c +++ b/components/esp_hw_support/sleep_modem.c @@ -14,7 +14,7 @@ #include "esp_sleep.h" #include "esp_check.h" #include "soc/soc_caps.h" -#include "esp_private/pm_impl.h" +#include "soc/rtc.h" #include "esp_private/sleep_modem.h" #include "esp_private/sleep_retention.h" #include "sdkconfig.h" diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 1d5322b5879..cc503c821ef 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -55,10 +55,6 @@ #include "hal/timer_ll.h" #endif -#if SOC_PM_SUPPORT_PMU_MODEM_STATE -#include "esp_private/pm_impl.h" -#endif - #if !SOC_PMU_SUPPORTED #include "hal/rtc_cntl_ll.h" #endif @@ -1218,15 +1214,13 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_m sleep_cache_suspend(); } #endif - // Restore CPU frequency + // Restore CPU frequency (Will fallback to rtc_clk_cpu_freq_set_config if PLL source is not configured.) + rtc_clk_cpu_freq_set_config_fast(&cpu_freq_config); #if SOC_PM_SUPPORT_PMU_MODEM_STATE && !SOC_PM_BBPLL_PD_IN_MODEM_STATE && !SOC_PM_MODEM_STATE_USE_XTAL if (pmu_sleep_pll_already_enabled()) { - rtc_clk_cpu_freq_to_pll_and_pll_lock_release(esp_pm_impl_get_cpu_freq(PM_MODE_CPU_MAX)); - } else -#endif - { - rtc_clk_cpu_freq_set_config(&cpu_freq_config); + rtc_clk_modem_pll_lock_release(); } +#endif esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CLK_READY, (void *)0); if (!deep_sleep) {