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feat(sha): add SM3 hardware support
Enable hardware SM3 digest support on ESP32-H4, ESP32-S31 and ESP32-C5 via the SHA peripheral (mode 14).
This commit is contained in:
committed by
Ashish Sharma
parent
320f344cd6
commit
7f413c914d
@@ -911,6 +911,10 @@ config SOC_SHA_SUPPORT_SHA512_T
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bool
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default y
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config SOC_SHA_SUPPORT_SM3
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bool
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default y
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config SOC_ECC_CONSTANT_TIME_POINT_MUL
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bool
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default y
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@@ -375,6 +375,7 @@
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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#define SOC_SHA_SUPPORT_SM3 (1)
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/*--------------------------- ECC CAPS ---------------------------------------*/
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#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
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@@ -815,6 +815,10 @@ config SOC_SHA_SUPPORT_SHA512_T
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bool
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default y
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config SOC_SHA_SUPPORT_SM3
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bool
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default y
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config SOC_ECC_CONSTANT_TIME_POINT_MUL
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bool
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default y
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@@ -352,6 +352,7 @@
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#define SOC_SHA_SUPPORT_SHA384 (1)
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#define SOC_SHA_SUPPORT_SHA512 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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#define SOC_SHA_SUPPORT_SM3 (1)
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/*--------------------------- ECC CAPS ---------------------------------------*/
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#define SOC_ECC_CONSTANT_TIME_POINT_MUL 1
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@@ -1091,6 +1091,10 @@ config SOC_SHA_SUPPORT_SHA512_T
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bool
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default y
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config SOC_SHA_SUPPORT_SM3
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bool
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default y
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config SOC_MPI_MEM_BLOCKS_NUM
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int
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default 4
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@@ -401,6 +401,7 @@
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#define SOC_SHA_SUPPORT_SHA512_224 (1)
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#define SOC_SHA_SUPPORT_SHA512_256 (1)
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#define SOC_SHA_SUPPORT_SHA512_T (1)
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#define SOC_SHA_SUPPORT_SM3 (1)
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/*--------------------------- MPI CAPS ---------------------------------------*/
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#define SOC_MPI_MEM_BLOCKS_NUM (4)
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