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Merge branch 'refactor/gpio_rom_func_rename_v6.0' into 'release/v6.0'

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refactor(rom/gpio): add 'rom_' prefix to GPIO ROM functions (v6.0)

See merge request espressif/esp-idf!43400
This commit is contained in:
morris
2025-11-20 21:35:13 +08:00
parent 0825f0f0cf 653e24f69f
commit 7f0f043e63
64 changed files with 556 additions and 562 deletions
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components/soc/esp32c2/register/soc/io_mux_reg.h
-3
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@@ -123,9 +123,6 @@
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 20
#define MAX_GPIO_NUM 24
#define DIG_IO_HOLD_BIT_SHIFT 0
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32c3/register/soc/io_mux_reg.h
+1 -3
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@@ -133,9 +133,7 @@
#define USB_INT_PHY0_DM_GPIO_NUM 18
#define USB_INT_PHY0_DP_GPIO_NUM 19
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 21
#define MAX_GPIO_NUM 25
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c5/register/soc/io_mux_reg.h
-3
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@@ -134,9 +134,6 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 28
#define MAX_GPIO_NUM 32
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32c6/register/soc/io_mux_reg.h
-3
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@@ -140,9 +140,6 @@
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32c61/register/soc/io_mux_reg.h
+1 -2
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@@ -110,8 +110,7 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 29
#define MAX_GPIO_NUM 33
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32h2/register/soc/io_mux_reg.h
-2
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@@ -152,8 +152,6 @@
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function
#define MAX_PAD_GPIO_NUM 27
#define MAX_GPIO_NUM 31
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h21/register/soc/io_mux_reg.h
+1 -2
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@@ -145,8 +145,7 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 18
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define MAX_PAD_GPIO_NUM 25
#define MAX_GPIO_NUM 29
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h4/register/soc/io_mux_reg.h
+1 -2
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@@ -138,8 +138,7 @@ extern "C" {
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 39
#define MAX_GPIO_NUM 39
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h
-2
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@@ -176,8 +176,6 @@
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
-2
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@@ -176,8 +176,6 @@
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32s2/register/soc/io_mux_reg.h
-2
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@@ -144,8 +144,6 @@
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32s3/register/soc/io_mux_reg.h
+2 -3
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@@ -154,9 +154,8 @@
#define XTAL32K_P_GPIO_NUM 15
#define XTAL32K_N_GPIO_NUM 16
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 48
#define MAX_GPIO_NUM 53
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)