Merge branch 'feat/support_lcd_on_s31' into 'master'

feat(lcd): support rgb and i80 lcd on s31

Closes IDF-14750, IDF-14751, IDF-14753, and IDF-14754

See merge request espressif/esp-idf!47312

components/soc/esp32s31/include/soc/Kconfig.soc_caps.in

@@ -39,6 +39,26 @@ config SOC_GPTIMER_SUPPORTED
     bool
     default y
 
+config SOC_LCDCAM_SUPPORTED
+    bool
+    default y
+
+config SOC_LCDCAM_I80_LCD_SUPPORTED
+    bool
+    default y
+
+config SOC_LCDCAM_RGB_LCD_SUPPORTED
+    bool
+    default y
+
+config SOC_LCD_I80_SUPPORTED
+    bool
+    default y
+
+config SOC_LCD_RGB_SUPPORTED
+    bool
+    default y
+
 config SOC_MCPWM_SUPPORTED
     bool
     default y

components/soc/esp32s31/include/soc/clk_tree_defs.h

@@ -161,6 +161,23 @@ typedef enum {
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;
 
+//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of LCD
+ */
+#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APLL}
+
+/**
+ * @brief Type of LCD clock source
+ */
+typedef enum {
+    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL,         /*!< Select APLL as the source clock */
+    LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
+} soc_periph_lcd_clk_src_t;
+
 //////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32s31/include/soc/periph_defs.h

@@ -14,6 +14,7 @@ extern "C" {
 
 typedef enum {
     /* HP peripherals */
+    PERIPH_LCD_CAM_MODULE,
     PERIPH_TIMG0_MODULE,
     PERIPH_TIMG1_MODULE,
     PERIPH_UHCI0_MODULE,

components/soc/esp32s31/include/soc/retention_periph_defs.h

@@ -61,10 +61,9 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MCPWM1       = 36,
     SLEEP_RETENTION_MODULE_MCPWM2       = 37,
     SLEEP_RETENTION_MODULE_MCPWM3       = 38,
-    SLEEP_RETENTION_MODULE_PCNT0        = 39,
-    SLEEP_RETENTION_MODULE_PCNT1        = 40,
-    SLEEP_RETENTION_MODULE_SDM0         = 41,
-    SLEEP_RETENTION_MODULE_JPEG         = 42,
+    SLEEP_RETENTION_MODULE_SDM0         = 39,
+    SLEEP_RETENTION_MODULE_LCDCAM       = 40,
+    SLEEP_RETENTION_MODULE_JPEG         = 41,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 43,

components/soc/esp32s31/include/soc/soc_caps.h

@@ -35,10 +35,12 @@
 #define SOC_DMA2D_SUPPORTED             1
 #define SOC_GPTIMER_SUPPORTED           1
 // #define SOC_PCNT_SUPPORTED              1      // TODO: [ESP32S31] IDF-14699
-// #define SOC_LCDCAM_SUPPORTED            1      // TODO: [ESP32S31] IDF-14722
+#define SOC_LCDCAM_SUPPORTED            1
 // #define SOC_LCDCAM_CAM_SUPPORTED        1      // TODO: [ESP32S31] IDF-14722
-// #define SOC_LCDCAM_I80_LCD_SUPPORTED    1      // TODO: [ESP32S31] IDF-14722
-// #define SOC_LCDCAM_RGB_LCD_SUPPORTED    1      // TODO: [ESP32S31] IDF-14722
+#define SOC_LCDCAM_I80_LCD_SUPPORTED    1
+#define SOC_LCDCAM_RGB_LCD_SUPPORTED    1
+#define SOC_LCD_I80_SUPPORTED           1
+#define SOC_LCD_RGB_SUPPORTED           1
 #define SOC_MCPWM_SUPPORTED             1
 #define SOC_TWAI_SUPPORTED              1
 #define SOC_TWAI_FD_SUPPORTED           1

components/soc/esp32s31/register/soc/lcd_cam_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0 OR MIT
  */
@@ -953,7 +953,7 @@ typedef union {
 } lcdcam_lc_reg_date_reg_t;
 
 
-typedef struct {
+typedef struct lcd_cam_dev_t {
     volatile lcdcam_lcd_clock_reg_t lcd_clock;
     volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
     volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
@@ -980,11 +980,12 @@ typedef struct {
     volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
     uint32_t reserved_074[34];
     volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
-} lcdcam_dev_t;
+} lcd_cam_dev_t;
 
+extern lcd_cam_dev_t LCD_CAM;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32s31/register/soc/reg_base.h

@@ -40,7 +40,7 @@
 #define DR_REG_SOC_ETM_BASE                       0x20393000
 #define DR_REG_TWAIFD0_BASE                       0x20394000
 #define DR_REG_TWAIFD1_BASE                       0x20395000
-#define DR_REG_LCD_CAM_BASE                       0x20396000
+#define DR_REG_LCDCAM_BASE                        0x20396000
 #define DR_REG_UHCI0_BASE                         0x20398000
 #define DR_REG_SYSTIMER_BASE                      0x20399000
 #define DR_REG_ZERO_DET_BASE                      0x2039A000