Merge branch 'refactor/regi2c_mst_clock_enable' into 'master'

refactor(regi2c): analog i2c mst clock should be enabled/disabled per usage

Closes IDF-10492 and IDF-10693

See merge request espressif/esp-idf!32682

components/esp_hw_support/include/esp_private/regi2c_ctrl.h

@@ -10,11 +10,50 @@
 #include "sdkconfig.h"
 #include "esp_rom_regi2c.h"
 #include "soc/regi2c_defs.h"
+#include "soc/soc_caps.h"
+#include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#ifdef BOOTLOADER_BUILD
+
+// For bootloader, the strategy is to keep the analog i2c master clock always enabled if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (in bootloader_hardware_init())
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+
+#else // !BOOTLOADER_BUILD
+
+#if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+// This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc.
+// Use reference count to manage the analog i2c master clock
+#define ANALOG_CLOCK_ENABLE() \
+      PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(true); \
+            } \
+      }
+
+#define ANALOG_CLOCK_DISABLE() \
+      PERIPH_RCC_RELEASE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(false); \
+            } \
+      }
+
+#else
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+#endif
+
+#endif // BOOTLOADER_BUILD
+
+// regi2c write/read requires analog i2c master clock enabled
+#define REGI2C_CLOCK_ENABLE()      ANALOG_CLOCK_ENABLE()
+#define REGI2C_CLOCK_DISABLE()     ANALOG_CLOCK_DISABLE()
+
 
 #define regi2c_read_reg_raw        esp_rom_regi2c_read
 #define regi2c_read_reg_mask_raw   esp_rom_regi2c_read_mask

components/esp_hw_support/modem_clock.c

@@ -18,6 +18,7 @@
 #include "hal/efuse_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
+#include "esp_private/regi2c_ctrl.h"
 
 // Please define the frequently called modules in the low bit,
 // which will improve the execution efficiency
@@ -118,7 +119,11 @@ static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context
 
 static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)
 {
-    regi2c_ctrl_ll_master_enable_clock(enable);
+    if (enable) {
+        ANALOG_CLOCK_ENABLE();
+    } else {
+        ANALOG_CLOCK_DISABLE();
+    }
 }
 
 static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable)

components/esp_hw_support/periph_ctrl.c

@@ -31,25 +31,25 @@ IRAM_ATTR void periph_rcc_exit(void)
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
 }
 
-uint8_t periph_rcc_acquire_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_acquire_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph];
 }
 
-void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ++ref_count;
     periph_rcc_exit();
 }
 
-uint8_t periph_rcc_release_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_release_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph] - 1;
 }
 
-void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ref_count;
     periph_rcc_exit();

components/esp_hw_support/port/esp32/include/soc/rtc.h

@@ -726,7 +726,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 4
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4  //!< Main XTAL, divided by 4
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32c2/include/soc/rtc.h

@@ -715,7 +715,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32c3/include/soc/rtc.h

@@ -784,7 +784,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32c5/rtc_clk.c

@@ -22,10 +22,7 @@
 #include "esp_private/sleep_event.h"
 #include "hal/efuse_hal.h"
 #include "soc/chip_revision.h"
-
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -133,27 +130,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -162,7 +145,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32c5/rtc_clk_init.c

@@ -79,6 +79,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+
     uint32_t hp_cali_dbias = get_act_hp_dbias();
     uint32_t lp_cali_dbias = get_act_lp_dbias();
 

components/esp_hw_support/port/esp32c6/include/soc/rtc.h

@@ -465,7 +465,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32c6/ocode_init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,10 +11,9 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
-
 static const char *TAG = "ocode_init";
 
 static void set_ocode_by_efuse(int ocode_scheme_ver)
@@ -57,6 +56,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -73,6 +73,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 

components/esp_hw_support/port/esp32c6/pmu_init.c

@@ -211,6 +211,7 @@ void pmu_init(void)
     /* Peripheral reg i2c power up */
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);

components/esp_hw_support/port/esp32c6/rtc_clk.c

@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -139,25 +139,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -166,7 +154,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32c61/ocode_init.c

@@ -11,7 +11,7 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
 // TODO: IDF-9303
@@ -58,6 +58,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -74,6 +75,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 

components/esp_hw_support/port/esp32c61/rtc_clk.c

@@ -20,10 +20,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -131,27 +128,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif  //SOC_MODEM_CLOCK_SUPPORTED
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -160,7 +143,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32h2/include/soc/rtc.h

@@ -462,7 +462,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32h2/rtc_clk.c

@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -155,25 +155,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -182,7 +170,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 

components/esp_hw_support/port/esp32p4/rtc_clk.c

@@ -21,6 +21,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/io_mux_reg.h"
 #include "esp_private/sleep_event.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -141,7 +142,9 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
 {
     /* Digital part */
     clk_ll_cpll_set_freq_mhz(cpll_freq);
+
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* CPLL CALIBRATION START */
     regi2c_ctrl_ll_cpll_calibration_start();
     clk_ll_cpll_set_config(cpll_freq, xtal_freq);
@@ -150,6 +153,7 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* CPLL CALIBRATION STOP */
     regi2c_ctrl_ll_cpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
 
     s_cur_cpll_freq = cpll_freq;
 }
@@ -362,34 +366,42 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
     }
 }
 
+static uint32_t rtc_clk_hp_root_get_freq_mhz(soc_cpu_clk_src_t clk_src)
+{
+    uint32_t source_freq_mhz = 0;
+    switch (clk_src) {
+    case SOC_CPU_CLK_SRC_XTAL:
+        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
+        break;
+    case SOC_CPU_CLK_SRC_CPLL:
+        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
+        break;
+    case SOC_CPU_CLK_SRC_RC_FAST:
+        source_freq_mhz = 20;
+        break;
+    default:
+        // Unknown HP_ROOT clock source
+        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
+        break;
+    }
+    return source_freq_mhz;
+}
+
 void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
+    if (source_freq_mhz == 0) {
+        // unsupported frequency configuration
+        abort();
+    }
     hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
-    uint32_t freq_mhz;
     clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator);
     if (div.denominator == 0) {
         div.denominator = 1;
         div.numerator = 0;
     }
-    switch (source) {
-    case SOC_CPU_CLK_SRC_XTAL: {
-        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
-        break;
-    }
-    case SOC_CPU_CLK_SRC_CPLL: {
-        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
-        break;
-    }
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        source_freq_mhz = 20;
-        break;
-    default:
-        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
-        abort();
-    }
-    freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
+    uint32_t freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
     *out_config = (rtc_cpu_freq_config_t) {
         .source = source,
         .source_freq_mhz = source_freq_mhz,
@@ -447,23 +459,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
 uint32_t rtc_clk_apb_freq_get(void)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
-    switch (source) {
-    case SOC_CPU_CLK_SRC_XTAL:
-        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
-        break;
-    case SOC_CPU_CLK_SRC_CPLL:
-        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
-        break;
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        source_freq_mhz = 20;
-        break;
-    default:
-        // Unknown HP_ROOT clock source
-        source_freq_mhz = 0;
-        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
-        break;
-    }
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
     uint32_t integer, numerator, denominator;
     clk_ll_cpu_get_divider(&integer, &numerator, &denominator);
     if (denominator == 0) {
@@ -549,6 +545,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
     clk_ll_apll_set_config(o_div, sdm0, sdm1, sdm2);
 
     /* calibration */
+    ANALOG_CLOCK_ENABLE();
     clk_ll_apll_set_calibration();
 
     /* wait for calibration end */
@@ -556,6 +553,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
         /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
         esp_rom_delay_us(1);
     }
+    ANALOG_CLOCK_DISABLE();
 }
 
 void rtc_dig_clk8m_enable(void)
@@ -590,6 +588,7 @@ TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
 void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
 {
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* MPLL calibration start */
     regi2c_ctrl_ll_mpll_calibration_start();
     clk_ll_mpll_set_config(mpll_freq, xtal_freq);
@@ -597,6 +596,8 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
     while(!regi2c_ctrl_ll_mpll_calibration_is_done());
     /* MPLL calibration stop */
     regi2c_ctrl_ll_mpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_mpll_freq = mpll_freq;
 }
 

components/esp_hw_support/port/esp32s2/include/soc/rtc.h

@@ -864,7 +864,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 4
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4  //!< Main XTAL, divided by 4
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp32s3/include/soc/rtc.h

@@ -842,7 +842,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**

components/esp_hw_support/port/esp_clk_tree_common.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -177,23 +177,23 @@ uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
 uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
 {
     switch (clk_ll_rtc_fast_get_src()) {
-    case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 //SOC_RTC_FAST_CLK_SRC_XTAL_D4
-        return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
-#elif CONFIG_IDF_TARGET_ESP32P4 //SOC_RTC_FAST_CLK_SRC_XTAL
-        return clk_hal_xtal_get_freq_mhz() * MHZ;
-#else //SOC_RTC_FAST_CLK_SRC_XTAL_D2
-        return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
-#endif
     case SOC_RTC_FAST_CLK_SRC_RC_FAST:
         return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
 #if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
     case SOC_RTC_FAST_CLK_SRC_LP_PLL:
         return clk_ll_lp_pll_get_freq_mhz() * MHZ;
 #endif
-#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL
     case SOC_RTC_FAST_CLK_SRC_XTAL:
         return clk_hal_xtal_get_freq_mhz() * MHZ;
+#endif
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
+        return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
+#endif
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
+    case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
+        return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
 #endif
     default:
         // Invalid clock source

components/esp_hw_support/regi2c_ctrl.c

@@ -20,32 +20,40 @@ static DRAM_ATTR __attribute__((unused)) const char *TAG = "REGI2C";
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_raw(block, host_id, reg_add, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_enter_critical(void)